XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 27

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Input Clock
The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
Input Clock Changes
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and out-
put clock.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 µs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time
LOCKED stays High and remains High when the clock is
restored.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
DS025-2 (v2.3) November 19, 2002
DLL-3S
DLL-1S
M
R
B
R
A
Figure 26: Virtex Series DLLs
DLL-3P
DLL-1P
M
B
R
A
DLL-2P
DLL-0P
M
B
R
A
DLL-2S
DLL-0S
M
B
R
A
Bottom Right
Half Edge
x132_14_100799
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates one to four clocks to
the output after the original shift, with no disruption to the
CLKDLL control.
Output Clocks
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Useful Application Examples
The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Standard Usage
The circuit shown in
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
Board Level De-Skew of Multiple Non-Virtex-E
Devices
The circuit shown in
system clock between a Virtex-E chip and other non-Vir-
tex-E chips on the same board. This application is com-
monly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.
Figure 27: Standard DLL Implementation
IBUFG
IBUF
CLKIN
CLKFB
RST
Figure 28
Figure 27
CLKDLL
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
can be used to de-skew a
resembles the BUFGDLL
BUFG
OBUF
ds022_028_121099
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