XC2V250-5CSG144I Xilinx Inc, XC2V250-5CSG144I Datasheet - Page 9

• Manufacturer Part Number: XC2V250-5CSG144I
• Description: IC FPGA VIRTEX-II 250K 144-CSBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V250-5CSG144I

• Number Of Labs/clbs: 384
• Total Ram Bits: 442368
• Number Of I /o: 92
• Number Of Gates: 250000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

DS031-2 (v3.5) November 5, 2007
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II™ I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
output driver supply voltage (V
standard (see
age (V
standard used. For exact supply voltage absolute maximum
ratings, see
All of the user IOBs have fixed-clamp diodes to V
ground. As outputs, these IOBs are not compatible or com-
pliant with 5V I/O standards. As inputs, these IOBs are not
normally 5V tolerant, but can be used with 5V I/O standards
when external current-limiting resistors are used. For more
details, see the “5V Tolerant I/Os“ Tech Topic at
inx.com
Table 3
trolled Impedance. See
(DCI), page
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031-2 (v3.5) November 5, 2007
Product Specification
CCAUX
Switch
Matrix
.
lists supported I/O standards with Digitally Con-
Figure 1: Virtex-II Input/Output Tile
DC Input and Output Levels
8.
Table 1
= 3.3 V) is required, regardless of the I/O
and
Table
Digitally Controlled Impedance
PAD4
PAD3
PAD2
PAD1
R
IOB
IOB
IOB
IOB
CCO
2). An auxiliary supply volt-
4
0
) is dependent on the I/O
Differential Pair
Differential Pair
in Module 3.
DS031_30_101600
CCINT
CCO
Figure
www.xil-
= 1.5V),
and to
www.xilinx.com
1.
Table 1: Supported Single-Ended I/O Standards
Notes:
1.
2.
3.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP-2X/AGP
IOSTANDARD
Attribute
V
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
SSTL18_I is not a JEDEC-supported standard.
N/R = no requirement.
CCO
of GTL or GTLP should not be lower than the termination
(2)
Virtex-II Platform FPGAs:
Note (1)
Note (1)
Output
V
Functional Description
1.5
1.5
2.5
2.5
3.3
3.3
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
3.3
CCO
CCO
to 1.5V.
Note (1)
Note (1)
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
CCO
Product Specification
N/R
Input
V
0.75
0.75
1.25
1.25
1.32
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
1.5
1.5
REF
(3)
Voltage (V
Termination
Module 2 of 4
Board
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.5
1.5
TT
)
1