EP2S180F1020C3N Altera, EP2S180F1020C3N Datasheet - Page 157

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EP2S180F1020C3N

Manufacturer Part Number
EP2S180F1020C3N
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S180F1020C3N

Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1883
EP2S180F1020C3N
Q2675539B

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Altera Corporation
April 2011
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (t
and hold time (t
to calculate t
Figure 5–3
Table 5–33. Stratix II Device Timing Model Status
t
t
SU
H
= – data delay from input pin to input register
EP2S130
EP2S180
= + data delay from input pin to input register
EP2S15
EP2S30
EP2S60
EP2S90
Device
+ micro setup time of the input register
– clock delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
shows the setup and hold timing diagram for input registers.
SU
and t
H
). The Quartus II software uses the following equations
H
timing for Stratix II devices input signals.
Preliminary
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Final
v
v
v
v
v
v
SU
5–21
)

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