EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 113

IC STRATIX II GX 130K 1508-FBGA

EP2SGX130GF1508I4N

Manufacturer Part Number
EP2SGX130GF1508I4N
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX130GF1508I4N

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2175

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Sunon
Quantity:
1 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA
Quantity:
80
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–73. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs
Notes to
(1)
(2)
Altera Corporation
October 2007
EP2SGX30C/D and EP2SGX60C/D devices only have two enhanced PLLs (5 and 6), but the connectivity from these
two PLLs to the global and regional clock networks remains the same as shown.
If the design uses the feedback input, you will lose one (or two, if FBIN is differential) external clock output pin.
Notes
Figure
(1),
2–73:
(2)
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
Figure 2–73
outputs and top and bottom CLK pins.
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
(2)
shows the global and regional clocking from enhanced PLL
(2)
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 6
PLL 5
(2)
(2)
Stratix II GX Device Handbook, Volume 1
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Stratix II GX Architecture
2–105

Related parts for EP2SGX130GF1508I4N