EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 73

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2010 Altera Corporation
Configuration
Table 1–50
Table 1–50. Configuration Mode Specifications for Arria II Devices
JTAG Specifications
Table 1–51
devices.
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52
and GZ devices.
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Passive serial
Fast passive parallel
Fast active serial (fast clock)
Fast active serial (slow clock)
Remote update only in fast AS mode
t
t
t
t
t
t
t
t
t
Dev_CLRn
JCP
JCH
JCL
JPSU (TDI)
JPSU (TMS)
JPH
JPCO
JPZX
JPXZ
Symbol
lists the configuration mode specifications for Arria II GX and GZ devices.
lists the JTAG timing parameters and values for Arria II GX and GZ
lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Programming Mode
Description
Description
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
8.5
—
—
17
—
Min
500
DCLK Frequency
Min
30
14
14
—
—
—
1
3
5
Typ
—
—
26
13
—
Typ
—
Max
—
—
—
—
—
—
11
14
14
Max
125
125
40
20
10
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Unit
Unit
s
1–65