ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 27

• Manufacturer Part Number: ADMCF341BR
• Description: IC DSP 3CH 12BIT MOT-CTRL 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Motor Controlr

Specifications of ADMCF341BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.
REV. B
Address (hex)
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFA
0x3FF9
0x3FF8
0x3FF7
0x3FF6
0x3FF5
0x3FF4
0x3FF3
0x3FF2
0x3FF1
0x3FF0
0x3FEF
BOOT
Name
SYSCNTL
MEMWAIT
TPERIOD
TCOUNT
TSCALE
SPORT0_RX_WORDS1
SPORT0_RX_WORDS0
SPORT0_TX_WORDS1
SPORT0_TX_WORDS0
SPORT0_CTRL_REG
SPORT0_SCLKDIV
SPORT0_RFSDIV
SPORT0_AUTOBUF_CTRL
SPORT1_CTRL_REG
SPORT1_SCLKDIV
SPORT1_RFSDIV
SPORT1_AUTOBUF_CTRL
MEMORY
ALWAYS READ 0
RESERVED
FLASH
Figure 22. Configuration of Flash Memory Registers
MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.
15
ALWAYS READ 0
15
15
0
0
0
CODE
15
1
RESERVED
14
14
14
0
0
0
14
0
Table XIII. DSP Core Registers
13
13
13
0
0
0
13
0
12
12
12
FLASH MEMORY DATA REGISTER HIGH (FMDRH)
0
FLASH MEMORY DATA REGISTER LOW (FMDRL)
0
0
12
0
STATUS 5
FLASH MEMORY ADDRESS REGISTER
11
11
11
0
0
FLASH MEMORY CONTROL REGISTER
0
11
0
10
10
10
0
0
10
0
0
–27–
0
0
0
9
0
9
9
0
9
[15 . . . 0]
[15 . . . 0]
Bits
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[7 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
DATA 23
8
0
8
0
8
0
8
0
ADDRESS 11
7
0
7
0
7
0
0
7
8
6
0
6
0
6
0
6
0
0
5
0
0
5
5
5
0
DATA 7
4
0
0
4
0
4
0
4
0
3
0
0
0
3
0
3
3
0
SPORT0 Multichannel Word 1 Receive
SPORT0 Multichannel Word 0 Receive
Function
System Control Register
Memory Wait State Control Register
Interval Timer Period Register
Interval Timer Count Register
Interval Timer Scale Register
SPORT0 Multichannel Word 1 Transmit
SPORT0 Multichannel Word 0 Transmit
SPORT0 Control Register
SPORT0 Clock Divide Register
SPORT0 Receive Frame Sync Divide
SPORT0 Autobuffer Control Register
SPORT1 Control Register
SPORT1 Clock Divide Register
SPORT1 Receive Frame Sync Divide
SPORT1 Autobuffer Control Register
2
0
2
0
2
0
2
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0x2080
0x2081
0x2082
0x2083
ADMC(F)341