Z8937320ASG Zilog, Z8937320ASG Datasheet - Page 4

• Manufacturer Part Number: Z8937320ASG
• Description: IC 20MHZ DSP OTP 64-VQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320ASG

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
PIN FUNCTIONS
EA2–EA0.
pins provide the External Register Address. This address
bus is driven during both internal and external accesses. One
of up to seven user-defined external registers is selected by
the processor for reads or writes. EXT7 is always reserved
for use by the processor.
ED15–ED0.
are the data bus for the user-defined external registers, and
are shared by Port0. These pins are normally tristated, ex-
cept when these registers are specified as destination reg-
isters in a write instruction to an external peripheral, or when
Port0 is enabled for output. This bus uses the control signals
RD/WR, DS, and WAIT, and address pins EA2–EA0.
DS
signal for the ED Bus. DS is active for transfers to/from ex-
ternal peripherals only.
RD/WR.
data direction signal for the External Data Bus. Data is avail-
able from the processor on ED15–ED0 when this signal and
DS are both Low.
WAIT
edge of the clock with appropriate setup and hold times. A
single wait-state can be generated internally by setting the
appropriate bits in the wait state register. The user must
drive this line if multiple wait states are required. This pin
is shared with Port2.
CLKI.
can be driven by a signal or connected to a 32 KHz crystal.
CLKO.
It is used for operation with a 32 KHz crystal and the PLL
to generate the system clock.
HALT
The processor continuously executes NOPs and the pro-
gram counter remains constant while this pin is held Low.
This pin offers an internal pull-up.
RESET
es the contents of the Program Counter (PC) onto the stack
and then fetches a new PC value from program memory ad-
dress 0FFCH after the RESET signal is released. The Status
register is set to all zeros. At power-up RAM and other reg-
isters are undefined, however, they are left unchanged with
subsequent resets. RESET can be asserted asynchronously.
AN0–AN3.
put pins. The analog input signal should be between VALO
and VAHI for accurate conversions.
are enabled, and the Counter/Timer is disabled, this pin pro-
4
. Data Strobe (output). This pin provides the data strobe
. Wait State (input). This pin is sampled at the rising
. Halt State (input). This pin stops program execution.
Clock (input). This pin is the clock circuit input. It
. Reset (input). This pin resets the processor. It push-
Clock (output). This pin is the clock circuit output.
Read/Write Select (output). This pin controls the
External Address Bus (output, latched). These
Analog Inputs (input). These are the analog in-
External Data Bus (input/output). These pins
VAHI.
provides the reference for the full scale voltage of the analog
input signals.
VALO.
provides the reference for the zero voltage of the analog in-
put signals.
AV
provided on separate pins to reduce digital noise in the an-
alog circuits.
Multifunction Pins.
ly offers a user-configurable I/O structure, which means
that most of the I/O pins offer dual functions. The function,
direction (input or output), and for output, the characteris-
tics (push-pull or open drain) are all under user-control, by
programming the configuration registers appropriately as
described in the I/O Ports section. The following share I/O
Port pins:
INT0–INT2.
These pins provide three of the eight interrupt sources to
the Interrupt Controller. Each is programmable to be rising-
edge or falling-edge triggered. The other five interrupt
sources are from the on-chip peripherals.
CLKOUT.
to the internal processor clock.
SDI.
input.
SDO.
output.
SS.
only. SS advises the SPI that it is the target of a serial transfer
from an external Master.
SCLK.
Master mode and an input in Slave mode.
UI0, UI1.
pins are directly tested by the conditional branch instruc-
tions. They can also be read as bits in the status register.
These are asynchronous input signals that require no special
c l o c k s y n c h r o n i z a t i o n . C o u n t e r / T i m e r 0 a n d
Counter/Timer1 may use either of these pins as input.
UI2.
Counter/Timer 2.
TMO0/UO0.
put). Counter/Timer 0 and Counter/Timer 1 can be pro-
grammed to provide output on this pin. When User Outputs
vides the complement of Status Register bit 5.
CC
Slave Select (input). This pin is used in SPI Slave Mode
User Input (input). This pin is the input to
Serial Data In (input). This pin is the SPI serial data
–AGND.
Serial Data Out (output). This pin is the SPI serial data
Analog High Reference Voltage (input). This pin
SPI Clock (output/input). This pin is an output in
Analog Low Reference Voltage (input). This pin
User inputs (input). These general-purpose input
System Clock (output). This pin provides access
External Interrupts (input, edge-triggered).
Counter/Timer Output or User Output 0 (out-
Filtered Analog Power and Ground must be
The Z89223/273/323/373 DSP fami-
DS000202-DSP0599
ZiLOG