Z8937320FSC Zilog, Z8937320FSC Datasheet - Page 48

• Manufacturer Part Number: Z8937320FSC
• Description: DSP 20MHZ 80-PQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320FSC

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-1128; 269-1128

SYSTEM CLOCK GENERATOR (Continued)
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
mined by the PLL Divisor value in the MSB of the Clock
Control Register, Bank15/EXT5:
VCO Frequency = 4 x PLL Divisor x PLL In Frequency.
The PLL Divisor value should be between 1 and156 to ob-
tain a VCO Frequency between 128 kHz and 20 MHz from
a 32-kHz input.
There are four options for PLL Out: VCO Out, VCO Out
divided by 2, VCO Out divided by four, or twice the crystal
frequency. This selection is determined by the PLL Out Se-
lect bits in the Clock Control Register.
Note: The PLL is designed and tested to operate with an input
Sleep Modes
The Z893x3 supports various Clock Modes to minimize de-
vice power consumption. The lowest power mode is Deep
Sleep in which the System Clock is stopped, and the VCO
and XTAL Oscillator are both turned off.
48
frequency of approximately 32 kHz. It is possible to
drive the input with a crystal or user-generated clock at
some other frequency, but the results are not guaranteed.
Bank 15/Ext 5 Reg
D15 D14 D13 D12 D11 D10 D9 D8
Figure 43. System Clock Control Register
D7 D6 D5 D4 D3 D2 D1 D0
Programmable PLL Divider Register
System Clock = Bits 15Ð8 x 4 x Crystal Frequency (32.768 kHz)
Wake-Up From Sleep Modes
The Wake-up Trigger Source is specified by bits 5 and 6
of the Clock Control Register. The polarity of the Wake-
up signal is defined by bit 7. Wake-up occurs when the
wake-up signal is toggled to the specified wake-up polarity.
Wake-up resumes operation starting from the reset vector
address in the same way the chip responds to an external
RESET.
Mode
Power-up/Reset
(default)
PLL Clock
Crystal Oscillator
Direct
External Clock Direct
Deep Sleep
(lowest power)
Table 23. Standard Clock Mode Summary
STOP_OSC
STOP_VCO
BYPASS_PLL
DSP (System) Clock Source
Recovery Source
STOP Recovery Level
0 : Low (Default setting after reset)
1 : High
0 : Oscillator Running
1 : Stop Oscillator
0 : VCO Running
1 : Stop VCO
0 : Clock Source is Oscillator
1 : Clock Source is VCO
00 : VCO Clock
01 : VCO Clock Divided by 2
10 : VCO Clock Divided by 4
11 : Twice the Crystal Frequency
00 : POR (Power-On Reset) or
01 : POR or Port 1, Bit 4 (SS)
10 : POR or Port 1, Bit 6 (UI0)
11 : POR or Port 2, Bit 0 or
Port 2, Bit 0 (INT0)
Port 1, Bit 4 or Port 1, Bit 6
XTAL,
XTAL,
XTAL
XTAL
CLKI
User
User
User
Src
XTAL
Stop
Osc.
DS000202-DSP0599
0
0
0
1
1
Stop
VCO
0
1
1
0
1
ZiLOG
Sys
Clk
Sel
0
1
0
0
1