Z8937320FSC00TR Zilog, Z8937320FSC00TR Datasheet - Page 52

• Manufacturer Part Number: Z8937320FSC00TR
• Description: IC DSP OTP 8K 80PQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320FSC00TR

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INSTRUCTION DESCRIPTIONS (Continued)
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
52
Inst.
LD
Notes:
When <dest> is <hwregs>, <dest> cannot be P.
When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn if <src> is EXTn,
When <src> is <accind> <dest> cannot be A.
MLD
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands
<regind>, the <bank switch> defaults to ON.
MPYA Multiply and
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank
switch> defaults to ON.
MPYS Multiply and
<dest> cannot be X if <src> is X, <dest> cannot be SR if <src> is SR.
Description
Load
destination
with source
Multiply
add
subtract
Synopsis
LD<dest>,<src>
MLD <src1>,<src2>
[,<bank switch>]
MPYA <src1>,<src2>
[,<bank switch>]
MPYS <src1>,<src2>
[,<bank switch>]
Operands
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memind>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<simm>
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memind>
<hwregs>,<regind>
<hwregs>,<hwregs>
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Words Cycles Examples
1
1
1
1
3
1
1
1
1
1
1
1
1
1
2
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LD A,X
LD A,D0:0
LD A,P0:1
LD A,@P1:1
LD A,@D0:0
LD A,124
LD 124,A
LD D0:0,EXT7
LD P1:1,#%FA
LD P1:1,EXT1
LD@P1:1,#1234
LD @P1:1+,X
LD Y,P0:0
LD SR,D0:0
LD PC,#%1234
LD X,@A
LD Y,@D0:0
LD A,@P0:0–LOOP
LD X,EXT6
MLD A,@P0:0+LOOP
MLD A,@P1:0,OFF
MLD @P1:1,@P2:0
MLD @P0:1,@P1:0,ON
MPYA A,@P0:0
MPYA A,@P1:0,OFF
MPYA @P1:1,@P2:0
MPYA@P0:1,@P1:0,ON
MPYS A,@P0:0
MPYS A,@P1:0,OFF
MPYS @P1:1,@P2:0
MPYS
@P0:1,@P1:0,ON
DS000202-DSP0599
ZiLOG