ADSP-2186MKCA-300 Analog Devices Inc, ADSP-2186MKCA-300 Datasheet - Page 13

• Manufacturer Part Number: ADSP-2186MKCA-300
• Description: IC DSP CONTROLLER 16BIT 144MBGA
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2186MKCA-300

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 75MHz
• Non-volatile Memory: External
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-MBGA, 144-Mini-BGA

Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control
registers. The ADSP-2186M has 8K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
DMOVLAY
0
1
2
Memory Mapped Registers (New to the ADSP-2186M)
The ADSP-2186M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2186M’s wait state and BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
15 14 13 12 11 10 9
FROM 0 TO 7)
FROM 0 TO 15)
1
15 14 13 12 11 10 9
BMWAIT
1
1
1
DWAIT
1
1
1
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
1
1
1
IOWAIT3
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
0
WAITSTATE CONTROL
1
1
Memory
Reserved
External Overlay 1
External Overlay 2
1
8
1
8
1
IOWAIT2
EXTERNAL
MEMORY
7
0
7
1
ALWAYS
ACCESSIBLE
AT ADDRESS
0 x 2000 – 0 x 3FFF
6
0
DATA MEMORY
DM OVLAY = 0
6
1
RESERVED
5
0
5
1
PFTYPE
0 = INPUT
1 = OUTPUT
IOWAIT1
4
0
4
1
3
0
ACCESSIBLE WHEN
DMOVLAY = 1
3
1
2
0
2
1
ACCESSIBLE WHEN
DMOVLAY = 2
IOWAIT0
1
0
1
1
0
0 x 0000 – 0 x 1FFF
0
0
1
DM(0x3FE6)
DM(0x3FFE)
Table IV. DMOVLAY Bits
A13
Not Applicable
0
1
0 x 0000 – 0 x 1FFF
0 x 0000 – 0 x 1FFF
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
I/O Space (Full Memory Mode)
The ADSP-2186M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
1
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
RESERVED
15 14 13 12 11 10 9
0
SET TO 0
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
1
0
ALWAYS BE WRITTEN WITH ZEROS.
0
NOTE:
1
SEE TABLE IV FOR DMOVLAY BITS
DMOVLAY = 1, 2
DATA MEMORY
EXTERNAL 8K
0
8160 WORDS
REGISTERS
A12:0
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
32 MEMORY
INTERNAL
MAPPED
0
1
SYSTEM CONTROL
RESERVED, ALWAYS
0
8
0
SET TO 0
7
0
0 x 3FFF
0 x 3FE0
0 x 3FDF
0 x 2000
0 x 1FFF
0 x 0000
ADDR
DISABLE BMS
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN MEMORY
6
0
STROBES ARE THREE-STATED
5
0
4
0
3
0
ADSP-2186M
PWAIT
PROGRAM MEMORY
WAIT STATES
2
1
1
1
0
1
DM(0x3FFF)