EPM3256AQC208-7N Altera, EPM3256AQC208-7N Datasheet - Page 26

• Manufacturer Part Number: EPM3256AQC208-7N
• Description: IC MAX 3000A CPLD 256 208-PQFP
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3256AQC208-7N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 158
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 3000A
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 158
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1989; EPM3256AQC208-7N

MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
Figure 10. MAX 3000A Timing Model
26
Delay
Input
t
I N
Delay
PIA
t
PIA
MAX 3000A device timing can be analyzed with the Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in
devices have predictable internal delays that enable the designer to
determine the worst–case timing of any design. The software provides
timing simulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAC
I C
EN
LAD
IOE
Expander Delay
Parallel
t
PEXP
Figure 11
Register
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
shows the timing relationship
Figure
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
10. MAX 3000A
X1
Altera Corporation
Delay
I/O
t
I O