ATF750LVC-15SC Atmel, ATF750LVC-15SC Datasheet - Page 4

IC CPLD 15NS 24SOIC

ATF750LVC-15SC

Manufacturer Part Number
ATF750LVC-15SC
Description
IC CPLD 15NS 24SOIC
Manufacturer
Atmel
Series
ATF750LVCr
Datasheet

Specifications of ATF750LVC-15SC

Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
3 V ~ 5.25 V
Number Of Macrocells
10
Number Of I /o
10
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF750LVC15SC
8. Bus-friendly Pin-keeper Input and I/Os
9. Input Diagram
10. I/O Diagram
4
ATF750LVC
All input and I/O pins on the ATF750LVC have programmable “pin-keeper” circuits. If acti-
vated, when any pin is driven high or low and then subsequently left floating, it will stay at that
previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels,
which cause unnecessary power consumption and system noise. The keeper circuits elimi-
nate the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the software compiler table for more
details. Once the pin-keeper circuits are disabled, normal termination procedures are required
for unused inputs and I/Os.
Table 1. Software Compiler Mode Selection
ATF750LVC (PPK)
ATF750LVC
Synario
DATA
OE
INPUT
PROTECTION
V
CIRCUIT
CC
V750CPPK
ESD
WinCupl
V750C
V
CC
100K
PROGRAMMABLE
PROGRAMMABLE
OPTION
OPTION
100K
V
CC
Pin-keeper Circuit
Disabled
Enabled
I/O
1447F–PLD–11/08

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