MT9172AP1 Zarlink, MT9172AP1 Datasheet - Page 20

• Manufacturer Part Number: MT9172AP1
• Description: Digital Network Interface Circuit 28-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9172AP1

• Package: 28PLCC
• Maximum Data Rate: 160 Kbps
• Transmission Media Type: Twisted Pair
• Power Supply Type: Analog
• Typical Supply Current: 10 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25
Notes:
AC Electrical Characteristics
C4
OSC1
F0
C4
ST-BUS
BIT CELLS
1
2
3
4
5
6
C4 Clock Period
C4 Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
10.24 MHz Clock Jitter (wrt C4)
2.0V
0.8V
3.0V
2.0V
1)
2)
C4
F0
When operating as a SLAVE the C4 clock has a 40% duty cycle.
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F
0 ns to t
Characteristics
2.0V
0.8V
2.0V
0.8V
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
C
=2.5xf
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
C4P
°
C4
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
C and are for design aid only: not guaranteed and not subject to production testing.
). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from
. However, the relative jitter must be less than J
Channel 31
†
Bit 0
- Clock Timing - DN Mode (Figures 16 & 17)
Channel 0
Sym.
t
t
t
t
t
Bit 7
C4W
F0W
C4P
F0H
F0S
J
t
F0S
C
Zarlink Semiconductor Inc.
t
MT9171/72
F0W
Min.
50
50
Channel 0
Bit 6
Φ
t
20
F0H
Typ.*
244
122
244
±15
C
(see Figure 17).
Max.
J
C
t
C4P
Units
ns
ns
ns
ns
ns
ns
t
C4W
In Master Mode - Note 1
Note 2
t
Test Conditions
C4W
Data Sheet