W9825G6DH-6I Winbond Electronics, W9825G6DH-6I Datasheet
W9825G6DH-6I
Specifications of W9825G6DH-6I
Related parts for W9825G6DH-6I
W9825G6DH-6I Summary of contents
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... Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 4M × 4 BANKS × 16 BITS SDRAM Publication Release Date: Apr. 24, 2008 - 1 - W9825G6DH Revision A12 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39 11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 40 11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 41 12. PACKAGE SPECIFICATION .................................................................................................... 42 12.1 54L TSOP II - 400 mil ................................................................................................... 42 13. REVISION HISTORY ................................................................................................................ 43 W9825G6DH Publication Release Date: Apr. 24, 2008 - 2 - Revision A12 ...
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... W9825G6DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words × 4 banks × 16 bits. Using pipelined architecture and 0.11 µm process technology, W9825G6DH delivers a data bandwidth 166M words per second (-6). To fully comply with the personal computer industrial standard, W9825G6DH is sorted into the following speed grades: -6/-6C/- 6I and -75/75I. The - 6 is compliant to the 166MHz/CL3 or 133MHz/CL2 specification. The – ...
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... AVAILABLE PART NUMBER PART NUMBER W9825G6DH-6 W9825G6DH-6C W9825G6DH-6I W9825G6DH-75 W9825G6DH75I 4. PIN CONFIGURATION DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQM W E CAS RAS CS BS0 BS1 A10/ SPEED SELF REFRESH GRADE CURRENT (MAX) 166MHz/CL3 or 3mA 133MHz/CL2 166MHz/CL3 3mA 166MHz/CL3 3mA 133MHz/CL3 ...
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... Ground for input buffers and logic circuit inside DRAM. Separated power from V for I/O Buffer immunity. Ground Separated ground from V for I/O Buffer immunity. No connection. (NC pin should be connected to GND or floating W9825G6DH DESCRIPTION , to improve DQ noise improve DQ noise SS Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... CO LUMN DECO DER CELL ARRAY BANK #0 SENSE AMPLIFIER DAT CIRCUIT CO LUMN DECO DER CELL ARRAY BANK #2 SENSE AMPLIFIER Publication Release Date: Apr. 24, 2008 - 6 - W9825G6DH CO LUMN DECO DER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 LDQM UDQM CO LUMN DECO DER CELL ARRAY ...
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... Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. pins must be ramp up simultaneously to the specified voltage when Q ). The maximum time that each bank can be held active is RRD - 7 - W9825G6DH RSC delay. WE pin RCD Publication Release Date:Apr. 24, 2008 Revision A12 has ) ...
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... RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop. W9825G6DH Publication Release Date: Apr. 24, 2008 - 8 - Revision A12 ...
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... Data Data Data Data Data BURST LENGTH (disturb address is A0) No address carry from (disturb addresses are A0 and A1) No address carry from (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS Publication Release Date:Apr. 24, 2008 - 9 - W9825G6DH BURST LENGTH Revision A12 ...
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... The period between the Auto Refresh command and the next command is specified has been satisfied. Issue of Auto-pecharge command is RP and t are satisfied. This is referred Publication Release Date: Apr. 24, 2008 - 10 - W9825G6DH . The bank undergoing WR , Data-in DAL (min). RAS Revision A12 ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. W9825G6DH . The input buffers need (min (min) ...
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... These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. CKEn-1 CKEn DQM BS0, 1 A10 W9825G6DH A0−A9 CS RAS CAS A11, A12 ...
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... CCQ OPR T - OPR T -55 ~ 150 STG T 250 SOLDER OUT SYMBOL MIN. TYP. V 3.0 3 3.0 3.3 CCQ SYMBOL CLK C IO Publication Release Date:Apr. 24, 2008 - 13 - W9825G6DH UNIT NOTES °C 1 °C 1 °C 1 ° MAX. UNIT NOTES MIN. MAX. UNIT - 3 3 6.5 ...
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... CC2P I IH CC2S I (Power Down mode) IL CC2PS I IH CC3 I (Power Down mode) IL CC3P I CC4 I CC5 I CC6 SYMBOL MIN I( O( Publication Release Date: Apr. 24, 2008 - 14 - W9825G6DH -75/75I UNIT NOTES MAX. 100 150 130 3, 4 200 180 MAX. UNIT NOTES 5 µA 5 µA ...
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... 1.5 1 0.8 0 1.5 1 0.8 0 1.5 1.5 CKS t 0.8 0.7 CKH t 1.5 1.5 CMS t 0.8 0.7 CMH REF RSC XSR Publication Release Date:Apr. 24, 2008 - 15 - W9825G6DH -6I UNIT NOTES MIN. MAX 100000 1000 6 1000 5 1.5 9 0.8 9 1.5 9 0.8 9 1.5 9 0 ...
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... RCD t 1 CCD RRD 7 1.5 CKS t 1 CKH t 1.5 CMS t 1 CMH t REF t 2 RSC t 75 XSR Publication Release Date: Apr. 24, 2008 - 16 - W9825G6DH UNIT NOTES MAX. nS 100000 1000 1000 5 5 Revision A12 ...
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... The t maximum can’t be more than 10nS for low frequency application 10. If clock transiton time t is longer than 1nS, [(t T SS ohms AC TEST LOAD and 1nS. T /2)-0.5]nS should be added to the parameter W9825G6DH 50 ohms 30pF Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... Command Input Timing Command Input Timing CLK RAS CAS WE A0-A12 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH t CKS - 18 - W9825G6DH CMH CMS t CKH Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... Read Timing CLK CS RAS CAS A12 BS0 Read Command Read CAS Latency Valid Data-Out Publication Release Date:Apr. 24, 2008 - 19 - W9825G6DH Valid Data-Out Burst Length Revision A12 ...
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... CKS CKH CKS Valid Data- CMS CMS CMH Valid Valid Data-Out Data-Out OPEN CKS CKH CKS Valid Valid Data-Out Data-Out Publication Release Date: Apr. 24, 2008 - 20 - W9825G6DH Valid Valid Data-in Data- Valid Valid Data-in Data- Valid Data-Out Valid Data-Out Revision A12 ...
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... AS AH A0-A12 Register set data BS0 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency "0" (Test Mode) A8 "0" Reserved A0 A9 Write Mode A0 A10 "0" A11 A0 "0" A12 "0" A0 Reserved BS0 A0 "0" BS1 A0 "0" W9825G6DH t RSC command A0 Burst Length Sequential A0 Interleave Reserved A0 1 ...
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... RAS t t RCD RCD RBb RAc RBb CBx RAc t AC aw0 aw2 aw3 bx0 bx1 bx2 aw1 t t RRD RRD Active Precharge Active Read Precharge - 22 - W9825G6DH RAS RAS t RCD RBd CAy RBd CBz bx3 cy0 cy1 cy2 cy3 t RRD Precharge Read ...
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... Bank # the internal precharge start timing RAS t RCD t RCD RAc CAy CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD Active AP* Read - 23 - W9825G6DH RAS RAS t RCD RAe RBd CBz RAe RBd bx2 bx3 cy0 cy1 cy2 cy3 t t RRD RRD Read ...
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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 t RRD Precharge Active Read - 24 - W9825G6DH RAS RCD RAc RAc CAz t AC by4 by5 by6 by7 CZ0 Active Read Precharge Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... RAS RP t RCD RBb RBb CBy ax3 ax4 ax0 ax2 ax5 ax6 ax7 by0 ax1 t RRD AP* Active Read * AP is the internal precharge start timing - 25 - W9825G6DH RAS t t RAS RP t RCD RAc CAz RAc t CAC t CAC by1 by4 by5 by6 CZ0 Active ...
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... Bank # RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write - 26 - W9825G6DH RAS RAS RP t RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 CZ2 Active Write Precharge Publication Release Date: Apr. 24, 2008 ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 by3 t RRD AP* Active Write * AP is the internal precharge start timing - 27 - W9825G6DH RAS t RCD RAb CAz RAc by5 by4 by6 by7 CZ0 CZ1 CZ2 Write Active AP* Publication Release Date:Apr. 24, 2008 ...
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... Bank # CCD CCD CCD t RAS t RAS CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 28 - W9825G6DH CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 Precharge Read AP* Publication Release Date: Apr. 24, 2008 Revision A12 23 ...
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... CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAx A11,A12 DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank # RAS CAy ax5 ax0 ax1 ax3 ay0 ax2 ax4 Write - 29 - W9825G6DH ay1 ay2 ay4 ay3 Precharge Publication Release Date:Apr. 24, 2008 Revision A12 23 ...
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... CAw A11,A12 DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank # RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 30 - W9825G6DH RAS RP CAx t AC bx0 bx1 bx3 bx2 Read AP* Publication Release Date: Apr. 24, 2008 Revision A12 23 ...
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... CAw A11,A12 DQM CKE aw1 aw2 DQ aw0 Active Bank #0 Write Bank #1 Bank #2 Idle Bank # RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 31 - W9825G6DH RAS RP RAc RAc bx1 bx3 bx2 AP* Active Publication Release Date:Apr. 24, 2008 Revision A12 23 ...
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... Auto Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM CKE DQ All Banks Auto Prechage Refresh W9825G6DH Auto Refresh (Arbitrary Cycle) Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... RP RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS Self Refresh Cycle No Operation / Command Inhibit Self Refresh Exit - 33 - W9825G6DH CKS t XSR Arbitrary Cycle Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... A0-A9, RBa CBv A11,A12 DQM CKE DQ Read Active Bank #0 Bank #1 Bank #2 Idle Bank # CBw CBx t AC av0 av1 av3 aw0 ax0 av2 Single Write - 34 - W9825G6DH CBz CBy t AC ay0 az1 az2 az3 az0 Read Publication Release Date: Apr. 24, 2008 Revision A12 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data CAa t CKS ax0 ax2 ax3 ax1 Read Precharge - 35 - W9825G6DH RAa RAa CAx CKS NOP Active Precharge Standby Power Down mode Publication Release Date:Apr ...
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... Act Act Act Act Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W9825G6DH Act Act AP Act (min). RAS Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... Write Command (c) burst length = 4 Write Command (d) burst length = 8 Write Command Act tRP AP Act tWR tRP AP Act tRP tWR Act tRP AP Act tWR tRP AP tWR tRP W9825G6DH Act tWR tRP Act AP Act Act tWR tRP Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... CAS Latency=2 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM D0 DQ (2) CAS Latency=3 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM Read Write Read Write Read Write Read Write Read Read Read Q0 Q1 Read W9825G6DH Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... CAS latency =3 Read Command DQ (2) Write cycle (a) CAS latency =2 Write Command DQM DQ (b) CAS latency =3 Write Command DQM BST BST BST Note: BST represents the Burst stop command PRCG PRCG PRCG tWR PRCG tWR W9825G6DH Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... CKE/DQM Input Timing (Write Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK CKE MASK ( CKE MASK ( W9825G6DH CKE MASK Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... CKE/DQM Input Timing (Read Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM Open ( W9825G6DH Open Open Publication Release Date:Apr. 24, 2008 Revision A12 ...
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... W9825G6DH MAX. Publication Release Date: Apr. 24, 2008 Revision A12 ...
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... Notes Characteristics and Operating Condition Revise I and I CC2S CC3P 14, 17 Characteristics table from 10mA to 15mA and remove AC Testing Conditions table in Notes 6 Modify -6I grade AC timing specification t 15 1.0nS to 0.8nS - 43 - W9825G6DH DESCRIPTION /t =2 RCD RP T min from IH min from IH and CH min is 0 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Important Notice Publication Release Date: Apr. 24, 2008 - 44 - W9825G6DH Revision A12 ...