IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet
IS43DR16640A-25DBLI
Specifications of IS43DR16640A-25DBLI
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IS43DR16640A-25DBLI Summary of contents
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... IS43/46DR81280A, IS43/46DR16640A 1Gb (x8, x16) DDR2 SDRAM FEATURES • Clock frequency up to 400MHz • 8 internal banks for concurrent operation • 4‐bit prefetch architecture • Programmable CAS Latency: 3, 4, 5, 6 and 7 • ...
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... IS43/46DR81280A, IS43/46DR16640A Package Ball‐out and Description DDR2 SDRAM (128Mx8) BGA Ball‐out (Top‐View) (8.00mm x 13.65mm Body, 0.8mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command ...
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... IS43/46DR81280A, IS43/46DR16640A DDR2 SDRAM (64Mx16) BGA Ball‐out (Top‐View) (8.00mm x 13.65mm Body, 0.8mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command control inputs A[12:0] Address BA[2:0] Bank Address ...
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... The DDR2 SDRAM is now ready for normal operation. Note: ...
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... DDR2 Mode Register (MR) Setting The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst ...
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... written after power‐up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1, and BA2, and HIGH on BA0, and controlling pins A0 – A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH ...
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... Therefore, the extended mode register must be programmed during initialization for proper operation. The extended mode register 2 is written by asserting LOW on CS, RAS, CAS, WE, BA0, BA2, and HIGH on BA1, while controlling pins A0‐A13. The DDR2 SDRAM ...
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IS43/46DR81280A, IS43/46DR16640A contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. Extended Mode Register 2 (EMR[2]) Diagram Address Mode Field Register BA2 0 BA1 1 BA0 0 (1) A13 0 (1) A12 0 (1) A11 0 (1) A10 SRFt ( ( ...
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... Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1, and BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. ...
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... CKE must be maintained HIGH while the DDRII SDRAM is in OCD calibration mode. 15. “X” means “Don’t Care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT ...
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... DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. ...
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... ODT (On‐Die Termination) The On‐Die Termination feature allows the DDR2 SDRAM to easily implement an internal termination resistance (Rtt). For the x8 option, ODT can be configured for DQ[7:0], DQS, DQS#, DM, RDQS, and RDQS# signals. For the x16 option, ODT can be configured for ...
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IS43/46DR81280A, IS43/46DR16640A ODT Timing for Precharge Power‐Down Mode Note: Both ODT to Power Down Endtry and Exit Latencies tANPD and tAXPD are not met, therefore Power‐Down Mode timings have to be applied. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00D, 8/17/2010 13 ...
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... Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less than ...
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IS43/46DR81280A, IS43/46DR16640A AC and DC Logic Input Levels Single‐ended DC Input Logic Level Symbol Parameter VIH(DC) DC input logic HIGH VIL(DC) DC input logic LOW Single‐ended AC Input logic level Symbol Parameter VIH(AC) AC input logic HIGH VIL(AC) AC input logic LOW Note: Refer to Overshoot and Undershoot Specification for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. AC Input Test Conditions Symbol VREF Input reference voltage VREF Input signal maximum peak to peak swing SLEW Input signal minimum slew rate Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. AC Input Test Signal Waveform V SWING(MAX) Falling Slew = ...
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IS43/46DR81280A, IS43/46DR16640A Differential Signal Level Waveform Differential AC Output Parameters Symbol Parameter VOX(AC) AC differential crosspoint voltage Note: The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Overshoot and Undershoot Specification AC Overshoot and Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS Note: Please refer to AC Overshoot and Undershoot Definition Diagram. AC Overshoot and Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ* Maximum undershoot area below VSSQ* Note: Please refer to AC Overshoot and Undershoot Definition Diagram. AC Overshoot and Undershoot Definition Diagram Volts ( ...
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... DRAM output slew rate specification applies to 667 MT/s speed bins. 8. Timing skew due to DRAM output slew rate mis‐match between DQS / DQS# and associated DQ’s is included in tDQSQ and tQHS specification. Output Capacitance ...
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IS43/46DR81280A, IS43/46DR16640A ODT DC Electrical Characteristics Parameter/Condition Rtt effective impedance value for EMRS(A6=0, A2=1); 75 ohm Rtt effective impedance value for EMRS(A6=1, A2=0); 150 ohm Rtt effective impedance value for EMRS(A6=A2=1); 50 ohm Deviation of VM with respect to VDDQ/2 Note: 1. Measurement Definition for Rtt(eff): Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively 2. Measurement Defintion for VM: Measure voltage (VM) at test pin (midpoint) with no load: ODT AC Electrical Characteristics and Operating Conditions Symbol Parameter/Condition tAOND ODT turn‐on delay tAON ODT turn‐on tAONPD ODT turn‐on (Power‐Down Mode) tAOFD ODT turn‐off delay tAOF ODT turn‐off tAOFPD ODT turn‐off (Power‐Down Mode) tANPD ODT to Power‐Down Mode Entry L:atency tAXPD ODT Power Down Exit Latency Notes: 1. ODT turn on time min is when the de vice leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from t AOND. ...
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IS43/46DR81280A, IS43/46DR16640A IDD Specifications and Conditions IDD Measurement Conditions Symbol Parameter/Condition Operating Current ‐ One bank Active ‐ Precharge: IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating Current ‐ One bank Active ‐ Read ‐ Precharge: IOUT = ...
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IS43/46DR81280A, IS43/46DR16640A IDD Specifications Symbol Configuration x8 IDD0 x16 x8 IDD1 x16 IDD2P x8/x16 IDD2N x8/x16 x8 IDD2Q x16 IDD3Pf x8/x16 IDD3Ps x8/x16 IDD3N x8/x16 x8 IDD4R x16 x8 IDD4W x16 IDD5B x8/x16 IDD5D x8/x16 IDD6 x8/x16 x8 IDD7 x16 Notes: ...
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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Row Cycle Time tRC Auto Refresh Row tRFC Cycle Time Row Active Time tRAS Row Active to Column Address tRCD Delay tRRD(x8) Row Active to Row Active Delay tRRD(x16) tFAW(x8) Four Activate Window tFAW(x16) Column Address to Column Address tCCD Delay Row Precharge Time tRP Write Recovery Time tWR Auto precharge Write recovery + Precharge tDAL Time tCK3 (CL=3) tCK4 (CL=4) Clock Cycle Time tCK5 (CL=5) ...
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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Input Setup Time (fast tIS slew rate) Input Hold Time (fast slew tIH rate) Input Pulse Width tIPW Write DQS High Level tDQSH Width Write DQS Low Level tDQSL Width CLK to First Rising Edge of tDQSS DQS‐In Data‐In Setup Time to tDS DQS‐In (DQ, DM) Data‐In Hold Time to tDH DQS‐In (DQ, DM) DQS falling edge from CLK tDSS rising Setup Time DQS falling edge from CLK tDSH rising Hold Time DQ & DM Pulse Width tDIPW Read DQS Preamble Time tRPRE Read DQS Postamble tRPST ...
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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol DQ to Low Impedance from tLZ(DQ) CK/CK# Mode Register Set Delay tMRD OCD Drive Mode Output tMOD Delay ODT Drive Mode Output Delay Exit Self refresh to Non‐Read tXSNR Command Exit Self refresh to Read tXSRD Command Exit Precharge Power Down to any Non‐Read Command Exit Active Power Down to tXARD Read Command Exit Active Power Down to Read Command (slow exit, tAXRDS low power) Minimum time clocks remains ON after CKE tDELAY asynchronously drops LOW CKE minimum high and low pulse width Average Periodic Refresh Interval (‐40°C ≤ T ≤ +85° C) C ...
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... A maximum of eight Auto‐Refresh commands can be posted to any given DDR2 SDRAM device. (Note: tRFC depends on DRAM density) 12. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter ...
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IS43/46DR81280A, IS43/46DR16640A Reference Loads, Slew Rates and Slew Rate Derating 1. Reference Load for Timing Measurements Figure AC Timing Reference Load represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). This load circuit is also used for output slew rate measurements. AC Timing Reference Load CK, CK# The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS#) signal. 2. Slew Rate Measurements a) Output Slew Rate Output slew rate is characterized under the test conditions as shown in the figure below. Output slew rate for falling and rising edges is measured between VTT ‐ 250 mV and VTT + 250 mV for single ended ...
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... IS43DR81280A‐3DBLI IS43DR16640A‐3DBLI IS43DR16640A‐3DBI 6‐6‐6 IS43DR81280A‐25EBLI IS43DR16640A‐25EBLI 5‐5‐5 IS43DR81280A‐25DBLI IS43DR16640A‐25DBLI = ‐40°C to +85°C A CL‐t ‐ ...
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IS43/46DR81280A, IS43/46DR16640A PACKAGE OUTLINE DRAWING 60-ball FBGA: Fine Pitch Ball Grid Array Outline (x8) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00D, 8/17/2010 units (mm) 27 ...
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IS43/46DR81280A, IS43/46DR16640A 84-ball FBGA: Fine Pitch Ball Grid Array Outline (x16) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00D, 8/17/2010 28 ...