IS45S16320B-7CTNA1 ISSI, Integrated Silicon Solution Inc, IS45S16320B-7CTNA1 Datasheet

Page 1

... IS42S86400B IS42S16320B, IS45S16320B 64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply ddq IS42/45S16320B 3.3V 3.3V IS42S86400B 3.3V 3.3V • LVTTL interface • Programmable burst length – ( full page) • Programmable burst sequence: Sequential/Interleave • ...

Page 2

... IS42S86400B, IS42/45S16320B DEVICE OVERVIEW The 512Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 536,870,912 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 134,217,728-bit bank is or- ganized as 8,192 rows by 1024 columns by 16 bits. Each of the x8's 134,217,728-bit banks is organized as 8,192 rows by 2048 columns by 8 bits. The 512Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK ...

Page 3

IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9, A11 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, ...

Page 4

IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command Column Address Strobe Command CAS 4 V ...

Page 5

IS42S86400B, IS42/45S16320B PIN CONFIGURATION 54-ball W-BGA for x16 (Top View) (11. 13.00 mm Body, 0.8 mm Ball Pitch) package code: B PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command ...

Page 6

... DQML and DQMH control the lower and upper bytes of the I/O buffers. In read mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot be written to the device. For IS42/45S16320B only. For IS42S86400B only. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the " ...

Page 7

IS42S86400B, IS42/45S16320B GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x16); A0-A9, A11 (x8) provides the starting column location. W hen A10 is HIGH, this command functions as an AUTO PRECHARGE command. W hen the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide valid data ...

Page 8

IS42S86400B, IS42/45S16320B COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H ...

Page 9

IS42S86400B, IS42/45S16320B CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 CKE n – ...

Page 10

IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Current State CS RAS CAS WE Idle ...

Page 11

IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Read with auto H × × Precharging L L ...

Page 12

IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Write Recovering H × × ...

Page 13

IS42S86400B, IS42/45S16320B CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

Page 14

IS42S86400B, IS42/45S16320B STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF SELF exit MRS IDLE CKE CKE ACT CKE Row Active CKE BST BST Read Write Read Write ...

Page 15

IS42S86400B, IS42/45S16320B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr ...

Page 16

IS42S86400B, IS42/45S16320B DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps (In Power-Down Mode) i Precharge Standby Current (2) dd2n (In Non Power-Down Mode) I Precharge Standby Current dd2ns (In Non Power-Down Mode) ...

Page 17

IS42S86400B, IS42/45S16320B AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width ch t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t ...

Page 18

IS42S86400B, IS42/45S16320B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac ...

Page 19

IS42S86400B, IS42/45S16320B AC TEST CONDITIONS Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com Rev. ...

Page 20

... With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100µs delay has been satisfied. All banks must be precharged. This will leave all banks in an idle state after which at least eight AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power unknown state. Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 21

IS42S86400B, IS42/45S16320B INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, ...

Page 22

IS42S86400B, IS42/45S16320B AUTO-REFRESH CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. ...

Page 23

IS42S86400B, IS42/45S16320B SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge ...

Page 24

... IS42S86400B, IS42/45S16320B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. MODE REGISTER DEFINITION BA1 BA0 A12 A11 A10 (1) Reserved Write Burst Mode ...

Page 25

... IS42S86400B, IS42/45S16320B BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected ...

Page 26

IS42S86400B, IS42/45S16320B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier ( 1), and provided that the relevant access times are met, the data will be valid by clock edge For example, assuming that the clock cycle time is such that all relevant access times are met READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving ...

Page 27

... IS42S86400B, IS42/45S16320B CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the t specification. Minimum t rcd rcd the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered ...

Page 28

... Data from any READ burst may be truncated with a sub- sequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge im- mediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided given system design, there may be a pos- sibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. 28 READ COMMAND CLK HIGH CKE CS ...

Page 29

IS42S86400B, IS42/45S16320B diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result ...

Page 30

IS42S86400B, IS42/45S16320B RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL ...

Page 31

IS42S86400B, IS42/45S16320B CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. ...

Page 32

IS42S86400B, IS42/45S16320B RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL ...

Page 33

IS42S86400B, IS42/45S16320B READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 34

IS42S86400B, IS42/45S16320B ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

Page 35

IS42S86400B, IS42/45S16320B READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW COLUMN m ...

Page 36

IS42S86400B, IS42/45S16320B READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

Page 37

IS42S86400B, IS42/45S16320B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. ...

Page 38

... The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command example is shown in WRITE to WRITE diagram. Data either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule as- sociated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Random WRITE Cycles, or each subsequent WRITE may be performed to a different bank. ...

Page 39

IS42S86400B, IS42/45S16320B WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 CLK WRITE NOP NOP BANK, COL n ...

Page 40

IS42S86400B, IS42/45S16320B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL ...

Page 41

IS42S86400B, IS42/45S16320B WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 NOP ...

Page 42

IS42S86400B, IS42/45S16320B WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 43

IS42S86400B, IS42/45S16320B WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 44

IS42S86400B, IS42/45S16320B ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

Page 45

IS42S86400B, IS42/45S16320B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time Clock Suspend During WRITE Burst T0 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ Clock Suspend During READ Burst T0 CLK CKE INTERNAL CLOCK COMMAND READ BANK a, ADDRESS ...

Page 46

IS42S86400B, IS42/45S16320B CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH A0-A9, A11, A12 COLUMN m ( ...

Page 47

IS42S86400B, IS42/45S16320B PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and ...

Page 48

IS42S86400B, IS42/45S16320B POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles ...

Page 49

... ADDRESS COL a DQM DQ CAS Latency - 3 (BANK n) Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered ...

Page 50

IS42S86400B, IS42/45S16320B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. WRITE With Auto Precharge interrupted by a READ T0 T1 CLK WRITE - AP COMMAND NOP BANK n BANK ...

Page 51

IS42S86400B, IS42/45S16320B SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 52

IS42S86400B, IS42/45S16320B SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 53

IS42S86400B, IS42/45S16320B READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ...

Page 54

IS42S86400B, IS42/45S16320B READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t ...

Page 55

IS42S86400B, IS42/45S16320B SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 56

IS42S86400B, IS42/45S16320B SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW DISABLE ...

Page 57

IS42S86400B, IS42/45S16320B WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW t t ...

Page 58

IS42S86400B, IS42/45S16320B WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

Page 59

... IS42S86400B-75ETLI 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn IS42S16320B-75ETLI 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn Automotive Range: - +85 o Frequency Speed (ns) Order Part No. 143 MHz 7 IS45S16320B-7TLA1 IS45S16320B-7CTNA1 54-Pin TSOPII, Cu leadframe plated with NiPdAu IS45S16320B-7BLA1 Notes: 1. Please contact ISSI for leaded part support. 2. Part numbers with "L" or "N" are lead free and RoHS compliant Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 = 3. Package 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn 54-ball BGA, SnAgCu balls ...

Page 60

IS42S86400B, IS42/45S16320B 60 Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 ...

Page 61

IS42S86400B, IS42/45S16320B Integrated Silicon Solution, Inc. — www.issi.com Rev. E 10/06/2010 61 ...

Page 62

IS42S86400B, IS42/45S16320B 6.50 ±0.1 3. Integrated Silicon Solution, Inc. — www.issi.com 10/06/2010 Rev. E ...