NL128102AC20-07 Renesas Electronics America, NL128102AC20-07 Datasheet

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NL128102AC20-07

Manufacturer Part Number
NL128102AC20-07
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of NL128102AC20-07

Lead Free Status / Rohs Status
Supplier Unconfirmed
Document No. EN0236EJ2V0DS00 (2nd edition)
Date Published April 1997 M
Printed in Japan
Vertical screen expansion (Multi-scan), Incorporated backlight with inverter
DESCRIPTION
amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. NL128102AC20-07 has
a built-in backlight/inverter.
color (more than 16 million colors) simultaneously and can display of SXGA, XGA, SVGA, VGA, VGA-TEXT,
PC-9801, NTSC, and PAL.
FEATURES
APPLICATIONS
NL128102AC20-07 is a TFT (thin film transistor) active matrix color liquid crystal display (LCD) comprising
The 33 cm diagonal display area contains 1280 1024 pixels and can input analog signals and can display full-
Analog RGB interface
Vertical screen expansion (Multi-scan) SXGA, XGA, SVGA, VGA, VGA-TEXT, PC-9801, NTSC, PAL
High luminous / Low reflection
Incorporated edge-light type backlight with inverter.
Engineering workstation (EWS), Personal computer (PC), Word processor
Display terminals for control system
New media
Monitors for process controller
33cm (13 type), 1280
DATA S H E ET
NL128102AC20-07
1024 pixels, Full color
TFT COLOR LCD MODULE
©
1996

Related parts for NL128102AC20-07

NL128102AC20-07 Summary of contents

Page 1

... DESCRIPTION NL128102AC20- TFT (thin film transistor) active matrix color liquid crystal display (LCD) comprising amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. NL128102AC20-07 has a built-in backlight/inverter. The 33 cm diagonal display area contains 1280 1024 pixels and can input analog signals and can display full- color (more than 16 million colors) simultaneously and can display of SXGA, XGA, SVGA, VGA, VGA-TEXT, PC-9801, NTSC, and PAL ...

Page 2

... CNTDAT CNTCLK CNTSTB CNTSEL POWC OFF GND V DDB BRTC BRTH BRTL ACA 1 GNDB 1 GNDB is connected to the module frame ground. 2 AMP LCD timing controller 1024 lines converter Inverter NL128102AC20-07 Analog H-driver 1920 lines TFT-LCD panel H:1280 3 ( V:1024 1920 lines Analog H-driver Backlight ...

Page 3

... Luminance 200 cd/m Signal system Analog RGB signals, Synchronous signals (Hsync, Vsync), Dot clock Supply voltage 3 Backlight Edge light type, Four cold cathode fluorescent lamps with inverter Power consumption 21.3 W (typ.) NL128102AC20-07 : Down side (6 o'clock) : Perpendicular 2 (typ.) 3 ...

Page 4

... Ratings –0.3 to +4.6 –0.3 to +14 –0.3 to +14 –0.3 to +5.5 –4.0 to +4.0 –7.0 to +7.0 – +50 95% relative humidity 85% relative humidity Absolute humidity shall not exceed Ta = 50˚C, 85% relative humidity level. NL128102AC20-07 Unit mm mm pixel mm mm – color g Unit Remarks 25˚C ...

Page 5

... Ta = 25˚ 0.4 V (MIN.). ICLK p dot-checkered pattern CLK input equivalent circuit CLK (2) Input video signals ( Parameter Symbol Video input voltages V IRGB Video input limits V -RGB Idc NL128102AC20-07 min. typ. max. 3.0 3.3 3.6 11.4 12.0 12.6 11.4 12.0 12.6 0 – 0.8 IL 2.2 – ...

Page 6

... Analog RGB inputs are independent from this power supply sequence. ( better for the timing between logic signals and Logic signals 0<t< DDB V DD POWC V CC Logic signals ) is turned ON / OFF without logic signals, unstable data will be displayed input, if POWC signal is controlled follows. CC NL128102AC20-07 Time 0< 0< is not input 0<t<30 ms ...

Page 7

... Japan Aviation Electronics Industry Limited (JAE) Pin No. Symbol Pin No DDB DDB DDB 4 GNDB 10 5 GNDB 11 6 GNDB note : N.C. (No Connection) should be open. NL128102AC20-07 <Figure from socket view> Symbol Symbol <Figure from socket view> • • • DESEL GND GND DE Symbol <Figure from socket view> ACA ...

Page 8

... CNTSTB 11 5 GND 12 6 CNTCLK 13 7 CPSEL note : N.C. (No Connection) should be open. <Connector location: Rear view> 1 CN3 11 8 Symbol <Figure from socket view> CLAMP 13 12 GND FIELD GND N.C. GND 6 CN1 1 Connector 12 insert direction CN2 1 13 CN4 1 NL128102AC20-07 • • • ...

Page 9

... V DDB DDB GNDB Ground for backlight (V GNDB is connected to the module frame ground. GND – Signal ground for logic / LCD driving (V (Connect to a system ground.) NL128102AC20-07 Description H or open : Default L : External control (TTL level) (TTL level) (TTL level) (TTL level mode ...

Page 10

... Please keep CNTSTB to be "L" during transferring data. Input data can be changed during power on, but LCD display may be disturbed. When the serial data are changed, we recommend that the backlight power is off using BRTC function. 10 NL128102AC20-07 type, and zero point of the resistor corre- BRTL ( curve) ...

Page 11

... Serial communication timing and waveform D0 CNTDAT CNTSTB CNTCLK Parameter Symbol CLK pulse width twck CLK frequency fclk DATA setup-time tdst DATA hold-time tdhl Latch-pulse width twlp Latch setup-time tlst Rise / fall time tr, tf CNTDATA CNTCLK CNTSTB NL128102AC20- D41 min. max. Unit MHz ...

Page 12

... Horizontal count number D42 HSE0 Horizontal count number (LSB) D43 MOD1 CLK frequency select D44 MOD0 CLK frequency select MSB : Most Significant Bit LSB : Least Significant Bit 12 NL128102AC20-07 Function See table 2 See table 3 See table 4 See table 5 See table 6 See table 7 See table 8 ...

Page 13

... This is horizontal line number for effecting VIDEO signal from Vsync-fall. note3 : The maximum vertical position is Vsync total. note4 : Vertical position is fixed when CNTSEL is "H" or "open". NL128102AC20-07 Display mode 1 SXGA 1.25 XGA 1.6 SVGA 2.0 VGA 2.5 PC98, VGA, TEXT – ...

Page 14

... NL128102AC20-07 note 5 :DA (6:0) means Delay 6 (D15 (D21) <EXAMPLE> DA (6:0)=00H D15 2AH D15 ...

Page 15

... V-3.0 V) So, the total delay time is 22. Table 5. CLK reverse signal CKS 0 Data is sampled on rising edge of CLK. 1 Data is sampled on falling edge of CLK. note 9: CKS is "0", when CNTSEL is "H" or "open". NL128102AC20-07 Prohibit 59H 6BH 7FH = 3 changing ambient temperature and CC 0.002 0.002 20ns = – ...

Page 16

... NL128102AC20-07 Horizontal position [CLK] (note10) Prohibit Prohibit • • Prohibit 110 111 • • 509 510 511 HSE1 HSE0 CLK number (note12 • • • ...

Page 17

... The horizontal magnification multiples the input clock (CLK). Input CLK = system CLK horizontal magnification Example : In case of SXGA, SVGA and PC-9801, CLK frequency can be decided as follows. SXGA : (system CLK (107.5 MHz)) SVGA : (system CLK (40.0 MHz)) NL128102AC20-07 Magnification Vertical 1024 1 1024 768 1.25 800 600 1 ...

Page 18

... NL128102AC20-07 Module serial-data setting HSE HD VD Calculation formula (A) (B) = (C) 1.0 (B) 1.0 = (C) 1.25 (B) 1.25 1.6 (B) 1.6 2.0 (B) 2.0 1.6 (B) 1.6 2.0 (B) 2 ...

Page 19

... SVGA MODE (800 600) Holizontal = Vertical = (c) VGA MODE (640 480) Holizontal = Vertical = (d) 9801 MODE (640 400) Holizontal = Vertical = NL128102AC20-07 1024 pixels) (e) VGA-TEXT MODE (720 1.25 (1280 pixels) 1.25 (960 pixels) Black display area Valid area (f) PAL MODE (640 (Ver. 280 1.6 (1280 pixels) 1 ...

Page 20

... NL128102AC20-07 Unit Remarks MHz SXGA standard – – – – s 64.603 kHz – CLK (typ.) – s – – CLK - s – ...

Page 21

... Without use serial communication (CNTSEL = "H" or OPEN) CLK GND 1 Hsync Vsync Hsync 1 2.2 V (min.) to 5.25 V (max (min.) to 0.8 V (max.) IL NL128102AC20-07 tc tch V IdcCLK tcrf tds tdh tdrf tda thch 1 thrf 1 tvrf thvh thvs 1 ICLK thcs 21 ...

Page 22

... Hsync Display period <Vertical> Vsync Display period (NTSC/PAL) Vsync Field First field Vsync Hsync Field 1H(min.) 1H(min thp thb thd tv tvp tvb tvd Second field First field First field 1H(min.) NL128102AC20-07 thf tvf Second field 1H(min.) ...

Page 23

... Exclude noises on analog RGB signal. Because during CLAMP = " L", the pedestal level of analog RGB signals is sampled. If noises are on the analog signals, luminance level of display is changed and the display becomes bad. NL128102AC20- [CLK] tC [ns 200 min. ...

Page 24

... SXGA mode 0 1 (CNTSEL="H" or "open" INVALID B Hsync CLK SXGA mode (CNTSEL="H" or "open" note 1 : The flat erea of video signal should be more than 5 msec. 24 Pixels 1023 tvb 1 Line thp thb 1 CLK 352 INVALID NL128102AC20- 1280 ) D ( 1023, 1280 ) 47 48 VALID (2, X) 353 (X, 3) ...

Page 25

... DELSEL="H" CLK DATA INVALID DE Hsync DE DATA INVALID Vsync Hsync DATA INVALID DE NL128102AC20-07 tds thpd VALID tvp+tvb VALID INVALID tdh INVALID INVALID 25 ...

Page 26

... Do not disassemble and / or reassemble LCD module not re-adjust variable resistor or switch etc. e When returning the module for repair or etc., Please pack the module not to be broken. We recommend to use the original shipping packages. 26 NL128102AC20-07 or less) to the pin of BRTH and BRTL. If the ...

Page 27

... The display condition of LCD module may be affected by the ambient temperature. The LCD module uses cold cathode tube for backlight. The optical characteristics, like luminance or uniformity, will change during life time. Uneven brightness and/or small spots may be noticed depending on different display patterns. NL128102AC20-07 27 ...

Page 28

... OUTLINE DRAWING : Front View (Unit in mm) (4) (5) (5) (4) 4- 3.5 note 1 : The values in parentheses are for reference. note 2 : The torque of mounting screw should be 0.392 N•m (4 kgf•cm) less. 28 NL128102AC20-07 255.0 0.5 245.0 0.5 211.0 0.3 (Bezel Opening) (205.82) (Active Area) 245.0 0.5 (5) (4) (5) ...

Page 29

... OUTLINE DRAWING : Rear View (Unit in mm) (88.5) note 1 : The values in parentheses are for reference. note 2 : The torque of mounting screw should be 0.392 N•m (4 kgf•cm) less. NL128102AC20-07 (55.0) (29.0) (97.1) 29 ...

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... NL128102AC20-07 ...

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Page 32

... NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. NL128102AC20-07 ...

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