LQ 9D011 Sharp Electronics, LQ 9D011 Datasheet - Page 6

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LQ 9D011

Manufacturer Part Number
LQ 9D011
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LQ 9D011

Lead Free Status / Rohs Status
Compliant
LQ9D011
TIMING CHARACTERISTICS OF INPUT SIGNALS
NOTES:
1. Make sure that timing of the signals are above data (standard
2. Data enable signal should be Low longer than one clock in
3. Input signal waveforms are shown in Figures 3a, 3b,and 3c.
Page 6
SYMBOL
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
VGA) to ensure right display position and display quality.
every horizontal period.
CH
CL
DS
DH
ES
H
HP
V
VP
HS
HD
VS
VD
VF
VB
C
Clock Frequency
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Signal Setup Time
Horizontal Sync Signal Cycle
Horizontal Sync Signal Pulse Width
Vertical Sync Signal Cycle
Vertical Sync Signal Pulse Width
Horizontal Signal Display Start
Horizontal Signal Display Period
Vertical Sync Signal Display Start
Vertical Sync Signal Display Period
Hsync-Vsync Phase Difference – Front
Hsync-Vsync Phase Difference – Back
PARAMETER
MODE
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
480
400
350
ALL
ALL
ALL
480
400
350
480
400
350
ALL
ALL
1
Figure 2. Input Signals and Display on Screen
480
1
2
3
30.58
.
.
.
MIN.
770
–10
.
10
10
1
1 2
1
5
5
5
0
1
1
.
.
2
2
16.7
14.3
14.3
1
25.175
31.78
(144)
.
TYP.
800
640
480
400
350
96
34
34
61
2
3
525
449
449
R
G
B
28.322
35.75
MAX.
900
TFT-LCD Module
LCD Data Sheet
ms
ms
ms
480
1
Clock
Clock
Clock
Clock
MHz
Line
Line
Line
Line
Line
Line
Line
UNIT
.
ns
ns
ns
ns
ns
ns
ns
640
.
s
640
Line
Line
Line
5706-2

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