LS029B4DN01 Sharp Electronics, LS029B4DN01 Datasheet - Page 18

• Manufacturer Part Number: LS029B4DN01
• Manufacturer: Sharp Electronics

Specifications of LS029B4DN01

• Lead Free Status / Rohs Status: Compliant

8-2-2 Data Update Mode (Multiple Lines)
SCS
SI
SCLK
Updates arbitrary multiple lines data. (M0=”H”)
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
M1: Frame inversion flag.
M2: All clear flag.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
GL(n-1)th line
* Data write period
* Data transfer period
DUMMY DATA(don't care)
tsSCS
tsSI
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
Data is being stored in 1
For example, during GL2nd line data transfer period, GL 2
Mode select period
Refer to 8-2-4) All Clear Mode to execute clear.
M0
When “L”, display mode (maintain memory internal data).
DUMMY DATA(don't care)
(3ck)
thSI
(3ck"Dummy" +9ck"Address" +12ck"Dummy"=24ck)
M1
M2
AG0
AG0
Date transfer period
st
AG1
latch block of binary driver on panel.
twSCLKL
AG2
AG8
Gate line address select period
AG3
DUMMY DATA(don't care)
twSCLKH
GL (n)th line
AG4
(9ck)
AG5
AG6
twSCSH
twSCSH
nd
AG7
D1
line address is latched and GL1st line data is transferred from 1
AG8
D2
GL 1st Line
Date write period
Dummy period
(240ck)
(12ck)
DUMMY DATA(don't care)
D238
D239
D240
D1
D2
D3
Date write period
D4
Date transfer period
(240ck)
DUMMY DATA(don't care)
(24ck)
D237
st
D238
latch to pixel internal memory circuit at the same time.
D239
D240
DUMMY DATA(don't care)
SPEC No.
LCY-12T09X02A
(3ck"Dummy" +9ck"Address" +12ck"Dummy"=24ck)
AG0
Date transfer period
thSCS
GL 2nd line
AG8
MODEL No.
LS029B4DN01
DUMMY DATA(don't care)
twSCSL
D1
D2
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