AD7742BRZ Analog Devices Inc, AD7742BRZ Datasheet - Page 7

• Manufacturer Part Number: AD7742BRZ
• Manufacturer: Analog Devices Inc

Specifications of AD7742BRZ

• Converter Function: VFC
• Full Scale Frequency: 2750
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (max): 5.25V
• Single Supply Voltage (min): 4.75V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: SOIC N
• Lead Free Status / Rohs Status: Compliant

TERMINOLOGY
INTEGRAL NONLINEARITY
For the VFC, Integral Nonlinearity (INL) is a measure of the
maximum deviation from a straight line passing through the
actual endpoints of the VFC transfer function. The error is
expressed in % of the frequency span:
OFFSET ERROR
This is a measure of the offset error of the VFC. Ideally, the
minimum output frequency (corresponding to minimum input
voltage) is 5% of f
offset error. It is expressed in terms of the error referred to the
input voltage. It is expressed in mV.
GAIN ERROR
This is a measure of the span error of the VFC. The gain is the
scale factor that relates the input V
gain error is the deviation in slope of the actual VFC transfer
characteristic from the ideal expressed as a percentage of the
full-scale span.
OFFSET ERROR DRIFT
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in V/ C.
GAIN ERROR DRIFT
This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of span)/ C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the VFC is affected by changes
in the supply voltage. Again, this error is referred to the input
voltage. The input voltage is kept constant and the V
is varied 5%. The ratio of the apparent change in input voltage
to the change in V
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the input of one
channel to a sine wave on the input of another channel. It is
measured in dBs.
COMMON-MODE REJECTION
For the AD7742, the output frequency should remain un-
changed provided the differential input remains unchanged
although its common-mode level may change. The CMR is the
ratio of the apparent change in differential input voltage to the
actual change in common-mode voltage. It is expressed in dBs.
REV. 0
Frequency Span = f
CLKIN
DD
is measured in dBs.
The deviation from this value is the
OUT(max)
IN
to the output f
– f
OUT(min)
OUT
DD
. The
supply
–7–
GENERAL DESCRIPTION
The AD7741/AD7742 are a new generation of CMOS synchro-
nous Voltage-to-Frequency Converters (VFCs) that use a
charge-balance conversion technique. The AD7741 is a single-
channel version and the AD7742 is a multichannel version. The
input voltage signal is applied to a proprietary programmable
gain front-end based around an analog modulator that converts
the input voltage into an output pulse train.
The parts also contain an on-chip +2.5 V bandgap reference
and operate from a single +5 V supply. A block diagram of the
AD7742 is shown in Figure 2.
Input Amplifier Stage
The buffered input stage for the analog inputs presents a high
impedance, allowing significant external source impedances.
The four analog inputs (V
range from +0.5 V to V
range and is relative to the GND pin.
In the case of the AD7742 multichannel part, a differential
multiplexer switches one of the differential input channels to the
VFC modulator. The multiplexer is controlled by two pins, A1
and A0. See Table I for channel configurations.
A1
0
0
1
1
Analog Input Ranges
The AD7741 has a unipolar single-ended input channel whereas
the AD7742 contains four input channels which may be con-
figured as two fully differential channels or as three pseudo-
differential channels. The AD7742 also has a X1/X2 gain
option on the front end. The channel and gain settings are
pin-programmable.
The AD7742 uses differential inputs to provide common-mode
noise rejection (i.e., the converted result will correspond to the
differential voltage between the two inputs). The absolute voltage
on both inputs must lie between +0.5 V and V
V
V
V
V
IN
IN
IN
IN
1
2
3
4
A0
0
1
0
1
Table I. AD7742 Input Channel Selection
INPUT
MUX
Figure 2. AD7742 Block Diagram
V
V
V
V
V
IN
IN
IN
IN
IN
SWITCHED
SWITCHED
(+)
1
2
3
1
CAPS
CAPS
DD
IN
– 1.75 V. This is an absolute voltage
1 through V
INTEGRATOR
V
V
V
V
V
IN
IN
IN
IN
IN
AD7741/AD7742
(–)
4
4
4
2
IN
4) each have a voltage
Type
Pseudo Differential
Pseudo Differential
Full Differential
Full Differential
COMPARATOR
DD
–1.75 V.
f
OUT