RPIXP2800BB Intel, RPIXP2800BB Datasheet - Page 64

• Manufacturer Part Number: RPIXP2800BB
• Manufacturer: Intel

Specifications of RPIXP2800BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IXP28XX Network Processor
QDR SRAM
4.4.5
4.4.5.1
4.4.5.2
4.4.6
64
accessed first and second last leading to a daisy-chain configuration. Alternatively, a via could be
inserted in between the two SRAMs to create a T-Topology configuration which might be the
proper choice.
QDR SRAM Input/Output Timing Specifications
The following sections describe the input and output timing requirements for the IXP28XX
network processor QDR I/O buffer. All timings are with respect to a 233-MHz clock and the QDR
interface running at 466 MT/s. The timing is referenced from the rising edge of C/C# or K/K# for
the receiver and the transmitter, respectively.
IXP2800 Input Timing
The IXP28XX network processor input timings provide for the setup and hold-time requirements
of the network processor’s receiver only when it is receiving data from the QDR SRAM (Driver)
during the READ cycle operation. The output timing needed for this operation for the driver side
(QDR SRAM), is described in the specification sheet of the SRAM provided by the SRAM
manufacturer.
For further information about IXP2800 input timing, refer to the Intel
Network Processors Datasheet.
IXP2800 Output Timing
The IXP28XX network processor output timings provide for the output timing requirements of the
network processor’s driver when it is sending data to the QDR SRAM (Receiver) in the
ADDRESS, WRITE, and CONTROL operations. The setup-and-hold time requirements of the
receiver (QDR SRAM) side needed for these operations is described in the specification sheet of
the SRAM provided by the SRAM manufacturer.
For further information regarding IXP2800 output timing, refer to the Intel
IXP2850 Network Processors Datasheet.
QDR Signal Group Package Trace Length
In order to obtain the best timing margin, trace length-match all signals to within ±25 mils
including the package substrate trace routing length. All QDR package trace lengths are provided
in
Table
35.
®
Hardware Design Guide
IXP2800 and IXP2850
®
IXP2800 and