54F169LMQB. National Semiconductor, 54F169LMQB. Datasheet - Page 2

• Manufacturer Part Number: 54F169LMQB.
• Manufacturer: National Semiconductor

Specifications of 54F169LMQB.

• Lead Free Status / Rohs Status: Not Compliant

Connection Diagrams
Unit Loading Fan Out
Functional Description
The ’F169 uses edge-triggered J-K type flip-flops and has
no constraints on changing the control or data input signals
in either state of the clock The only requirement is that the
various inputs attain the desired state at least a setup time
before the rising edge of the clock and remain valid for the
recommended hold time thereafter The parallel load opera-
tion takes precedence over other operations as indicated in
the Mode Select Table When PE is LOW the data on the
P
the clock In order for counting to occur both CEP and CET
must be LOW and PE must be HIGH the U D input then
determines the direction of counting The Terminal Count
(TC) output is normally HIGH and goes LOW provided that
Pin Names
CEP
CET
CP
P
PE
U D
Q
TC
0
0
–P
0
–P
–Q
3
3
inputs enters the flip-flops on the next rising edge of
3
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
DIP SOIC and Flatpak
Pin Assignment for
Description
TL F 9488–1
HIGH LOW
50 33 3
50 33 3
1 0 1 0
1 0 2 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
2
U L
CET is LOW when a counter reaches zero in the Count
Down mode or reaches 15 for the ’F169 in the Count Up
mode The TC output state is not a function of the Count
Enable Parallel (CEP) input level Since the TC signal is de-
rived by decoding the flip-flop states there exists the possi-
bility of decoding spikes on TC For this reason the use of
TC as a clock signal is not recommended (see logic equa-
tions below)
1) Count Enable
2) Up (’F169) TC
3) Down TC
54F 74F
20 A
20 A
20 A
20 A
20 A
20 A
Output I
b
b
Input I
1 mA 20 mA
1 mA 20 mA
e
b
b
b
b
b
b
IH
OH
Q
0 6 mA
1 2 mA
0 6 mA
0 6 mA
0 6 mA
0 6 mA
e
0
e
I
IL
I
CEP
OL
Pin Assignment
Q
Q
1
0
for LCC
CET
Q
Q
1
2
Q
Q
PE
3
2
(Down)
Q
3
(Up)
CET
TL F 9488– 2
CET