SC16C650BIB48.128 NXP Semiconductors, SC16C650BIB48.128 Datasheet - Page 19

• Manufacturer Part Number: SC16C650BIB48.128
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIB48.128

• Number Of Channels: 1
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16C650B_4
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level.
Table 10.
Bit
7:6
5:4
3
Symbol
FCR[7] (MSB),
FCR[6] (LSB)
FCR[5] (MSB),
FCR[4] (LSB)
FCR[3]
FIFO Control Register bits description
Rev. 04 — 14 September 2009
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C650B will issue a transmit empty interrupt when
the number of characters in FIFO drops below the selected trigger level.
Refer to
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C650B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
are no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C650B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Table
UART with 32-byte FIFOs and IrDA encoder/decoder
12.
Table
11.
SC16C650B
© NXP B.V. 2009. All rights reserved.
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