L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 38

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Register Description
Register Functions/Settings
Table 21. Control Register—Address 0
1. The reset bit is automatically cleared upon completion of the reset sequence. This bit is set to 1 during reset.
2. This is the master enable for digital and analog loopback as defined by the standard. The exact type of loopback is determined by the loopback control
3. The speed selection address 0 bits 13 and 6 may be used to configure the link manually. Setting these bits has no effect unless address 0 bit
4. When this bit is cleared, the link configuration is determined manually.
5. Setting this bit isolates the PHY from the MII, GMII, or RGMII interfaces.
6. This bit may be used to configure the link manually. Setting this bit has no effect unless address 0 bit 12 is clear.
7. Enables IEEE 22.2.4.1.9 collision test.
38
register (address 19).
12 is clear.
Bit
5:0
15
14
13
12
11
10
9
8
7
6
Reset
Loopback
Speed Selection
(LSB)
Autonegotiation
Enable
Powerdown
Isolate
Restart Autonegotia-
tion
Duplex Mode
Collision Test
Speed Selection
(MSB)
Reserved
Name
(continued)
1 = PHY reset.
0 = Normal operation.
1 = Enable loopback.
0 = Disable loopback.
Bit 6,13.
11 = Reserved.
10 = 1000 Mbits/s.
01 = 100 Mbits/s.
00 = 10 Mbits/s.
1 = Enable autonegotiation process.
0 = Disable autonegotiation process.
1 = Powerdown.
0 = Normal operation.
1 = Isolate PHY from MII.
0 = Normal operation.
1 = Restart autonegotiation process.
0 = Normal operation.
1 = Full duplex.
0 = Half duplex.
1 = Enable collision test.
0 = Disable collision test.
See bit 13.
Control Register
Description
—
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
SC
SC
SPEED_1000
See bit 13.
Default
September 2007
0
0
1
0
0
0
1
0
0
LSI Corporation
Notes
—
—
—
1
2
3
4
5
6
7
3