S2065A Applied Micro Circuits Corporation, S2065A Datasheet - Page 7

• Manufacturer Part Number: S2065A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2065A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

October 13, 2000 / Revision G
The following figures illustrate the broad range of
transmit data clocking options supported by the
S2065.
Figure 6 demonstrates the flexibility afforded by the
S2065. A low jitter reference is provided directly to
the S2065 at either 1/10 or 1/20 the serial data rate.
This ensures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TCLKx clock, which is provided back to the S2065,
other than that they remain within 3ns of the phase
relationship established at reset.
The S2065 also supports the traditional REFCLK
(TBC) clocking found in Fibre Channel and Gigabit
Ethernet applications and is illustrated in Figure 7.
This approach imposes significant challenges in
maintaining timing margins on the designer.
Half Rate Operation
The S2065 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2065
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus, the S2065 can support
Fibre Channel and serial backplane functions at both
full and 1/2 the VCO rate.
Figure 6. DIN Data Clocking with TCLK
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
ASIC
MAC
TCLKO
DINx[0:7]
TCLKx
VCO/10 or VCO/20
OSCILLATOR
REFCLK
S2065
REF
PLL
8B/10B Coding
The S2065 provides 8B/10B line coding for each chan-
nel. The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10-bit transmission character. The characters
defined by this code ensure that short run lengths and
enough transitions are present in the serial bit stream
to make clock recovery possible at the receiver. The
encoding also greatly increases the likelihood of de-
tecting any single or multiple errors that might occur
during the transmission and reception of data
The 8B/10B transmission code includes D-characters,
used for data transmission, and K-characters, used for
control or protocol functions. Each D-character and K-
character has a positive and a negative parity version.
The parity of each codeword is selected by the en-
coder to control the running disparity of the data
stream. K-character generation is controlled individu-
ally for each channel using the KGENx input. When
KGEN is asserted, the data on the parallel input is
mapped into the corresponding control character. The
parity of the K-character is selected to minimize run-
ning disparity in the serial data stream. Table 2 lists
the K characters supported by the S2065 and identi-
fies the mapping of the DIN[7:0] bits to each character.
1
Figure 7. FC/GE REFCLK DIN Clocking
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
ASIC
MAC
TCLKO
DINx[0:7]
TCLKx
OSCILLATOR
S2065
REFCLK
VCO/10
REF
PLL
1
S2065
.
7