TS68EN360VA25L E2V, TS68EN360VA25L Datasheet - Page 74

• Manufacturer Part Number: TS68EN360VA25L
• Manufacturer: E2V

Specifications of TS68EN360VA25L

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

8.4
74
Ethernet on QUICC
0886C–HIREL–04/08
The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs,
two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot assigner, three par-
allel ports, a parallel interface port, four independent baud rate generators, and fourteen serial DMA
channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer high-speed transfers,
32-bit data movement, buffer chaining, and independent request and acknowledge logic. The RISC con-
troller may access the IDMA registers directly in the buffer chaining modes. The QUICC IDMAs are
similar to, yet enhancements of, the one IDMA channel found on the TS68302.
The four general-purpose timers on the QUICC are functionally similar to the two general-purpose timers
found on the TS68302. However, they offer some minor enhancements, such as the internal cascading
of two timers to form a 32-bit timer. The QUICC also contains a periodic interval timer in the SIM60,
bringing the total to five on-chip timers.
The Ethernet protocol is available only on the Ethernet version of the QUICC called the TS68EN360.
The non-Ethernet version of the QUICC is the MC68360. The term “QUICC” is the overall device name
that denotes all versions of the device.
The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet operation
on any of the four SCCs. Due to performance reason not ass SCCs can be configured as Ethernet con-
troller at the same time. The TS68EN360 is not restricted only to Ethernet operation. HDLC, UART, and
other protocols may be used to allow dynamic switching between protocols. See Appendix A Serial Per-
formance for available SCC performance.
When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs the full set
of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions (see
1)
Figure 8-1.
CTS = CLSN
CD = RENA
RRJCT
RSTRT
PERIPHERAL BUS
Ethernet Block Diagram
RXD
IMB
RECEIVER
CONTROL
UNIT
RECEIVE
SHIFTER
DATA
FIFO
REGISTERS
CONTROL
TRANSMIT
SHIFTER
DATA
FIFO
TRANSMITTER
CONTROL
UNIT
TXD
INTERNAL CLOCKS
AND DEFER
GENERATOR
SLOT TIME
COUNTER
CLOCK
RTS = TENA
CD = RENA
CTS = CLSN
e2v semiconductors SAS 2008
TS68EN360
RX CLOCK
TX CLOCK
Figure 8-