CY7C027V-15AI Cypress Semiconductor Corp, CY7C027V-15AI Datasheet
CY7C027V-15AI
Specifications of CY7C027V-15AI
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CY7C027V-15AI Summary of contents
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... Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 32K x 16 organization (CY7C027V) • 64K x 16 organization (CY7C028V) • 32K x 18 organization (CY7C037V) • 64K x 18 organization (CY7C038V) • 0.35-micron CMOS for optimum speed/power • High-speed access: 15/20/25 ns • ...
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... LBL 10 UBL 11 CE0L 12 CE1L 13 SEML 14 VCC 15 R/WL 16 OEL 17 GND 18 GND 19 I/O15L 20 I/O14L 21 I/O13L 22 I/O12L 23 I/O11L 24 I/O10L Note: 5. This pin is NC for CY7C027V. Document #: 38-06078 Rev. *A 100-Pin TQFP (Top View CY7C028V (64K x 16) CY7C027V (32K x 16 CY7C027V/028V CY7C037V/038V A9R 74 A10R 73 A11R 72 A12R ...
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... Note: 6. This pin is NC for CY7C037V. Document #: 38-06078 Rev. *A 100-Pin TQFP (Top View CY7C038V (64K x 18) CY7C037V (32K x 18 CY7C037V/038V CY7C037V/038V -15 15 125 35 10 µA CY7C027V/028V CY7C037V/038V A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R 69 A14R [6] 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 SEMR 62 ...
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... CC GND NC Architecture The CY7C027V/028V and CY7037V/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C027V/028V and CY7037V/038V provide on-chip ar- bitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t of each other, the busy logic will determine PS which port has access ...
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... Com’l. 80 120 [8] Ind. Com’l. 10 250 [8] Ind. Com’l. 75 105 [9] [8] Ind. Test Conditions ° MHz 3.3V CC CY7C027V/028V CY7C037V/038V [7] .................................. –0. +0.5V CC Ambient Temperature V CC ° ° 3.3V ± 300 +70 C ° ° 3.3V ± 300 mV – +85 C CY7C037V/038V -20 -25 Typ. Max. ...
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... CY7C037V/038V -15 Min. Max. Min less than t and t is less than t HZCE LZCE HZOE CY7C027V/028V CY7C037V/038V 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) -20 -25 Max. Min. Max. Unit ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C027V/028V and CY7037V/038V are designed with battery backup in mind. Data retention voltage and supply cur- rent are guaranteed over temperature. The following rules en- sure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
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... To access RAM SEM = Document #: 38-06078 Rev. *A [20, 21, 22 DATA VALID [20, 23, 24] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027V/028V CY7C037V/038V t OHA t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...
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... Document #: 38-06078 Rev. *A [25, 26, 27, 28 [28] t PWE [31] t HZWE t SD [25, 26, 27, 33 SCE LOW CE or SEM and a LOW PWE HZWE . CY7C027V/028V CY7C037V/038V [31] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on SD PWE Page [+] Feedback ...
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... SPS Document #: 38-06078 Rev. *A [34] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [35, 36, 37] MATCH t SPS MATCH = CE = HIGH. L CY7C027V/028V CY7C037V/038V t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW Document #: 38-06078 Rev. *A [38 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C027V/028V CY7C037V/038V BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06078 Rev. *A [39] ADDRESS MATCH BLC ADDRESS MATCH BLC [39 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027V/028V CY7C037V/038V t BHC t BHC Page [+] Feedback ...
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... Notes: 40. t depends on which enable pin ( deasserted first 41 depends on which enable pin (CE or R/W INS INR L Document #: 38-06078 Rev [40 READ 7FFF (FFFF for CY7C028V/38V) [41] t INR t WC [40 READ 7FFE (FFFF for CY7C028V/38V) [41] t INR ) is asserted last. L CY7C027V/028V CY7C037V/038V Page [+] Feedback ...
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... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027V/028V CY7C037V/038V –I/O Operation 8 Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only ...
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... Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C027V-15AC CY7C027V-15AXC 20 CY7C027V-20AC CY7C027V-20AXC 25 CY7C027V-25AC CY7C027V-25AXC 64K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AC CY7C028V-15AXC 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3V Asynchronous Dual-Port SRAM Speed ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C027V/028V CY7C037V/038V ...
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... Document History Page Document Title: CY7C027V/CY7C028V/CY7C037V/CY7C038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 REV. ECN NO. Issue Date ** 237626 6/30/04 *A 259110 See ECN Document #: 38-06078 Rev. *A Orig. of Change Description of Change YDT Converted data sheet from old spec 38-00670 to conform with new data sheet ...