MCP4822-E/P Microchip Technology, MCP4822-E/P Datasheet - Page 17

• Manufacturer Part Number: MCP4822-E/P
• Description: IC DAC 12BIT DUAL W/SPI 8DIP
• Manufacturer: Microchip Technology

Specifications of MCP4822-E/P

• Number Of Converters: 2
• Package / Case: 8-DIP (0.300", 7.62mm)
• Settling Time: 4.5µs
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Resolution: 12 bit
• Interface Type: Serial (3-Wire, SPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
5.1
The MCP482X family is designed to interface directly
with the SPI port, available on many microcontrollers,
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional and, thus, data
cannot be read out of the MCP482X devices. The CS
pin must be held low for the duration of a write com-
mand. The write command consists of 16 bits and is
used to configure the DAC’s control and data latches.
Register 5-1 details the input registers used to
configure and load the DAC
Refer
Characteristics tables for detailed input and output tim-
ing specifications for both Mode 0,0 and Mode 1,1
operation.
REGISTER 5-1:
© 2005 Microchip Technology Inc.
bit 15
bit 14
bit 13
bit 12
bit 11-0
Upper Half:
bit 15
Legend
R = Readable bit
-n = Value at POR
W-x
A/B
to
SERIAL INTERFACE
Overview
A/B: DAC
1
0
GA: Output Gain Select bit
1
0
SHDN: Output Power-down Control bit
1
0
D11:D0: DAC Data bits
12-bit number “D” which sets the output value. Contains a value between 0 and 4095.
= Write to DAC
= Write to DAC
= 1x (V
= 2x (V
= Output Power-down Control bit
= Output buffer disabled, Output is high-impedance
—
Figure 1-1
W-x
Don’t Care
—
Lower Half:
bit 7
A
OUT
OUT
W-x
WRITE COMMAND REGISTER
D7
or DAC
= V
= 2 * V
and
B
A
REF
A
B
W-x
GA
Select bit
and DAC
the
REF
* D/4096)
W-x
D6
W = Writable bit
1 = bit is set
* D/4096)
AC
B
SHDN
W-0
registers.
Electrical
W-x
D5
W-x
D11
W-x
D4
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
5.2
The write command is initiated by driving the CS pin
low, followed by clocking the four configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the selected DAC’s input registers. The
MCP482X devices utilize a double-buffered latch struc-
ture to allow both DAC
synchronized with the LDAC pin, if desired. Upon the
LDAC pin achieving a low state, the values held in the
DAC’s input registers are transferred into the DACs’
output registers. The outputs will transition to the value
and held in the DAC
All writes to the MCP482X devices are 16-bit words.
Any clocks past 16 will be ignored. The most signifi-
cant four bits are configuration bits. The remaining 12
bits are data bits. No data can be transferred into the
device with CS high. This transfer will only occur if 16
clocks have been transferred into the device. If the
rising edge of CS occurs prior, shifting of data into the
input registers will be aborted.
MCP4821/MCP4822
W-x
D10
Write Command
W-x
D3
W-x
D9
X
register.
W-x
D2
A
’s and DAC
x = bit is unknown
W-x
D8
bit 8
W-x
D1
DS21953A-page 17
B
’s outputs to be
W-x
D0
bit 0