DS1859E-050 Maxim Integrated Products, DS1859E-050 Datasheet - Page 4

• Manufacturer Part Number: DS1859E-050
• Description: IC RES TEMP 50/50K 3MON 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1859E-050

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.85 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
AC ELECTRICAL CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
4
SCL Clock Frequency
Bus Free Time Between STOP and
START Condition
Hold Time (Repeated)
START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Data Hold Time
Data Setup Time
START Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
EEPROM Write Time
CC
_____________________________________________________________________
= 2.85V to 5.5V, T
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
SDA and SCL are connected to V
Full Scale is user programmable. The maximum voltage that the MON inputs read is approximately Full Scale, even if the volt-
age on the inputs is greater than Full Scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
See the Typical Operating Characteristics.
A fast-mode device can be used in a standard-mode system, but the requirement t
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
PARAMETER
A
= -40°C to +95°C, unless otherwise noted. See Figure 6.)
SYMBOL
t
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
SU:STA
t
t
t
f
HIGH
LOW
SCL
BUF
C
t
t
t
W
R
F
B
CC
and all other input signals are connected to well-defined logic levels.
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Notes 9, 10)
Standard mode (Notes 9, 10)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Notes 9, 11, 12)
Standard mode (Notes 9, 11, 12)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 13)
Standard mode (Note 13)
Fast mode (Note 13)
Standard mode (Note 13)
Fast mode
Standard mode
(Note 13)
(Note 14)
CONDITIONS
CC
is switched off.
RMAX
SU:DAT
+ t
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
SU:DAT
MIN
100
250
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.0
0
0
0
0
> 250ns must then be met. This
= 1000ns + 250ns = 1250ns
B
B
B
B
TYP
10
CC
voltage.
MAX
1000
400
100
300
300
300
400
0.9
20
UNITS
kHz
ms
pF
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs