MCP4017T-503E/LT Microchip Technology, MCP4017T-503E/LT Datasheet - Page 34

• Manufacturer Part Number: MCP4017T-503E/LT
• Description: IC DGTL POT 50K 128TAPS SC70-6
• Manufacturer: Microchip Technology

Specifications of MCP4017T-503E/LT

• Package / Case: SC-70-6, SC-88, SOT-363
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 50K
• Number Of Pots: Single
• Taps Per Pot: 128
• Resistance: 50 KOhms
• Wiper Memory: Volatile
• Buffered Wiper: Buffered
• Digital Interface: Serial (2-Wire, I2C)
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Supply Current: 0.045 mA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: 7 Bit Single I2C Digital Rheostat
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Tolerance: 20 %
• End To End Resistance: 50kohm
• Track Taper: Linear
• No. Of Steps: 128
• Resistance Tolerance: ± 20%
• Supply Voltage Range: 1.8V To 5.5V
• Control Interface: I2C
• No. Of Pots: Single
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP4017T-503E/LTTR

MCP4017/18/19
5.2
I
•
•
•
•
•
•
Figure 5-8
5.2.1
The Start bit (see
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 5-2:
5.2.2
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see
FIGURE 5-3:
5.2.3
The A bit (see
device to the Master device. Depending on the context
of the transfer sequence, the A bit may indicate
different things. Typically the Slave device will supply
an A response after the Start bit and 8 “data” bits have
been received. The A bit will have the SDA signal low.
FIGURE 5-4:
DS22147A-page 34
2
C bit definitions include:
SDA
SCL
SDA
SCL
Start Bit
Data Bit
Acknowledge (A) Bit
Repeated Start Bit
Stop Bit
Clock Stretching
SDA
SCL
I
2
S
S
shows the waveform for these states.
C Bit Definitions
START BIT
DATA BIT
ACKNOWLEDGE (A) BIT
Figure
8
Figure
D0
5-4) is a response from the Slave
Figure
Start Bit.
Data Bit.
Acknowledge Waveform.
5-2) indicates the beginning of
1st Bit
1st Bit
5-3).
9
A
2nd Bit
2nd Bit
If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
high.
If an error condition occurs (such as an A instead of A)
then an START bit must be issued to reset the
command state machine.
TABLE 5-1:
5.2.4
The Repeated Start bit (see
current
communicating with the current Slave Device without
releasing the I
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5:
Waveform.
SDA
General Call
Slave Address
valid
Slave Address
not valid
Bus Collision
SCL
Note 1: A bus collision during the Repeated Start
Event
Master
REPEATED START BIT
• SDA is sampled low when SCL goes
• SCL goes low before SDA is asserted
condition occurs if:
from low to high.
low. This may indicate that another mas-
ter is attempting to transmit a data "1".
2
C bus. The Repeated Start condition is
A
A
A
N.A.
Acknowledge
Bit Response
MCP4017/18/19 A / A
RESPONSES
Device
Repeat Start Condition
© 2009 Microchip Technology Inc.
Figure
wishes
I
or a “Don’t Care” if
the collision occurs
on the Masters
“Start bit”.
Sr = Repeated Start
2
C Module Resets,
5-5) indicates the
Comment
to
1st Bit
continue