MCP41050-I/SN Microchip Technology, MCP41050-I/SN Datasheet - Page 22

• Manufacturer Part Number: MCP41050-I/SN
• Description: IC POT DIGITAL 50K 1CH SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP41050-I/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 800 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 50K
• Number Of Pots: Single
• Taps Per Pot: 256
• Resistance: 50 KOhms
• Buffered Wiper: Buffered
• Digital Interface: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 340 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Description/function: 256 Step SPI 50k Ohm with SPI Interface
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP41XXX/42XXX
5.8
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
FIGURE 5-5:
DS11195C-page 22
SCK
CS†
SO‡
SI
Using the MCP41XXX/42XXX in
SPI Mode 1,1
†
‡
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
X
1
Don’t
Care
Bits
Timing Diagram for SPI Mode 1,1 Operation.
2
X
COMMAND BYTE
Command
C1
3
Data is always latched in
on the rising edge of SCK.
Bits
C0
4
First 16 bits Shifted out will always be zeros
5
X
Don’t
Care
Bits
X
6
P1* P0
Channel
7
Select
Bits
8
D7
9
10
D6
11
D5
Data is always clocked out the SO
pin after the falling edge of SCK.
New Register Data
DATA BYTE
12
D4
13
D3
14
D2
15
D1
16
D0
X
2003 Microchip Technology Inc.
Data Registers are
loaded on rising
edge of CS. Shift
register is loaded
with zeros at this time.
SO pin will always
drive low when CS
goes high.