TDA8783HL/C4,151 NXP Semiconductors, TDA8783HL/C4,151 Datasheet - Page 11

• Manufacturer Part Number: TDA8783HL/C4,151
• Description: IC ADC 10BIT 40MSPS 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: Analog-to-Digital Interfacer

Specifications of TDA8783HL/C4,151

• Resolution (bits): 10 b
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -20°C ~ 75°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3606; 935266803151; TDA8783HLBE-S

Philips Semiconductors
Notes
1. More information about CDS related signals is available in the following figures: The clamp current for pin CPCDS is
2. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise
3. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the
2002 Oct 23
Z
I
ADC clamp control DAC (see Fig.8)
V
V
Z
I
OFE
Digital outputs (f
V
V
I
t
t
Serial interface
f
OFDOUT
DACOUT
OZ
o(h)
o(d)
SCLK(max)
OFDOUT
DACOUT
DACOUT(p-p)
DACOUT
OH
OL
40 Msps, 10-bit analog-to-digital
interface for CCD cameras
SYMBOL
given in Fig. 9, clamp current for pins IND and INP in Fig 10 and for clamp current for pin V
output amplitude is shown in Fig. 14
contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise
is taken into account as no signal is input. Figure15 gives noise figure graphs with signal input.
output delay timings (t
LOOP
additional 8-bit control DAC
(OFD) output impedance
OFD output current drive
ADC clamp 10-bit control DAC
output voltage (peak-to-peak
value)
DC output voltage
ADC clamp control DAC output
impedance
DAC output current drive
maximum offset error of
DAC + ADC clamp loop
HIGH-level output voltage
LOW-level output voltage
output current in 3-state mode
output hold time
output delay time
maximum frequency of serial
interface
CLK
= 40 MHz; C
PARAMETER
o(d)
), see Fig.5.
L
= 20 pF); note 3
static
code 0
code 1023
static
code 0
code 1023
I
I
0 V < V
C
C
C
C
C
C
OH
OL
L
L
L
L
L
L
= 20 pF; V
= 10 pF; V
= 20 pF; V
= 10 pF; V
= 20 pF; V
= 10 pF; V
= 1 mA
= 1 mA
11
CONDITIONS
o
< V
CCO
CCO
CCO
CCO
CCO
CCO
CCO
= 5 V
= 5 V
= 3 V
= 3 V
= 2.5 V
= 2.5 V
V
0
8
5
20
CCO
MIN.
0.5
2000
1
1.5
2.5
17
15
20
17
22
18
ref
TYP.
5
5
in Fig 11. The CDS
Product specification
TDA8783
50
250
50
V
0.5
+20
23
21
29
25
33
28
MAX.
CCO
V
V
V
LSB
LSB
V
V
ns
ns
ns
ns
ns
ns
ns
MHz
UNIT
A
A
A