AD7686CRM Analog Devices Inc, AD7686CRM Datasheet - Page 19

• Manufacturer Part Number: AD7686CRM
• Description: IC ADC 16BIT 500KSPS 10MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7686CRM

• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7686CBZ - BOARD EVALUATION FOR AD7686
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is generally used when multiple AD7686s are
connected to an SPI-compatible digital host. A connection
diagram example using two AD7686 devices is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers.
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
SDI(CS1)
SDI(CS2)
ACQUISITION
SDO
CNV
SCK
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
AD7686
D15
Figure 38. CS Mode 4-Wire, No Busy Indicator Serial Interface Timing
CNV
SCK
1
Figure 37. CS Mode 4-Wire, No Busy Indicator Connection Diagram
t
HSDO
D14
SDO
2
D13
3
t
DSDO
t
SCKL
t
SCKH
Rev. B | Page 19 of 28
14
SDI
t
SCK
AD7686
15
D1
CNV
SCK
t
CYC
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7686 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th
SCK falling edge or when SDI goes high, whichever occurs first,
SDO returns to high impedance and another AD7686 can
be read.
16
D0
ACQUISITION
SDO
t
ACQ
D15
17
DATA IN
CLK
CS2
CS1
CONVERT
DIGITAL HOST
D14
18
30
31
D1
32
D0
t
DIS
AD7686