MX7705EWE+T Maxim Integrated Products, MX7705EWE+T Datasheet - Page 22

• Manufacturer Part Number: MX7705EWE+T
• Description: IC ADC 16BIT 2CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MX7705EWE+T

• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The byte-wide communications register is bidirectional
so it can be written and read. The byte written to the
communications register indicates the next read or write
operation on the selected register, the power-down
mode, and the analog input channel (Table 6). The
DRDY bit indicates the conversion status.
0/DRDY: (Default = 0) Communication-Start/Data-Ready
Bit. Write a 0 to the 0/DRDY bit to start a write operation to
the communications register. If 0/DRDY = 1, then the
device waits until a 0 is written to 0/DRDY before continu-
ing to load the remaining bits. For a read operation, the
0/DRDY bit shows the status of the conversion. The
DRDY bit returns a 0 if the conversion is complete and
the data is ready. DRDY returns a 1 if the new data has
been read and the next conversion is not yet complete. It
has the same value as the DRDY output pin.
RS2, RS1, RS0: (Default = 0, 0, 0) Register-Select Bits.
RS0, RS1, and RS2 select the next register to be
accessed as shown in Table 7.
R/W: (Default = 0) Read-/Write-Select Bit. Use this bit to
select if the next register access is a read or a write
operation. Set R/W = 0 to select a write operation or set
R/W = 1 for a read operation on the selected register.
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Figure 10. Register Summary
22
DOUT
*THE TEST REGISTER IS USED FOR FACTORY TESTING ONLY.
DIN
______________________________________________________________________________________
COMMUNICATIONS REGISTER
OFFSET REGISTER (24 BITS)
RS2 RS1 RS0
CLOCK REGISTER (8 BITS)
SETUP REGISTER (8 BITS)
DATA REGISTER (16 BITS)
TEST REGISTER (8 BITS)*
GAIN REGISTER (24 BITS)
Communications Register
REGISTER
SELECT
DECODER
PD: (Default = 0) Power-Down Control Bit. Set PD = 1
to initiate power-down mode. Set PD = 0 to take the
device out of power-down mode. If CLKDIS = 0, CLKOUT
remains active during power-down mode to provide a
clock source for other devices in the system.
CH0, CH1: (Default = 0, 0) Channel-Select Bit. Write to
the CH0 and CH1 bits to select the conversion channel or
to access the calibration data shown in Table 8. The cali-
bration coefficients of a particular channel are stored in
one of the three offset and gain-register pairs in Table 8.
Set CH1 = 1 and CH0 = 0 to evaluate the noise perfor-
mance of the part without external noise sources. In this
noise evaluation mode, connect AIN1- to an external volt-
age within the allowable common-mode range.
The byte-wide setup register is bidirectional, so it can
be written and read. The byte written to the setup regis-
ter sets the calibration modes, PGA gain, unipolar/bipo-
lar mode, buffer enable, and conversion start (Table 9).
MD1, MD0: (Default = 0, 0) Mode-Select Bits. See
Table 10 for normal operating mode, self-calibration,
zero-scale calibration, or full-scale calibration-mode
selection.
G2, G1, G0: (Default = 0, 0, 0) Gain-Selection Bits. See
Table 11 for PGA gain settings.
B/U: (Default = 0) Bipolar/Unipolar Mode Selection. Set
B/U = 0 to select bipolar mode. Set B/U = 1 to select
unipolar mode.
BUF: (Default = 0) Buffer-Enable Bit. For unbuffered
mode, disable the internal buffer of the MX7705 to reduce
power consumption by writing a 0 to the BUF bit. Write a
1 to this bit to enable the buffer. Use the internal buffer
when acquiring high source-impedance input signals.
FSYNC: (Default = 1) Filter-Synchronization/
Conversion-Start Bit. Set FSYNC = 0 to begin calibration
or conversion. The MX7705 performs free-running con-
versions while FSYNC = 0. Set FSYNC = 1 to stop con-
verting data and to hold the nodes of the digital filter, the
filter-control logic, the calibration-control logic, and the
analog modulator in a reset state. The DRDY output does
not reset high if it is low (indicating that valid data has not
yet been read from the data register) when FSYNC goes
high. To clear the DRDY output, read the data register.
The byte-wide clock register is bidirectional, so it can
be written and read. The byte written to the setup regis-
ter sets the clock, filter first-notch frequency, and the
output data rate (Table 12).
MXID: (Default = 1) Maxim-Identifier Bit. This is a read-
only bit. Values written to this bit are ignored.
Setup Register
Clock Register