AD9233BCPZ-105 Analog Devices Inc, AD9233BCPZ-105 Datasheet - Page 23

• Manufacturer Part Number: AD9233BCPZ-105
• Description: IC ADC 12BIT 105MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9233BCPZ-105

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 105M
• Number Of Converters: 3
• Power Dissipation (max): 350mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 105MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9233-125EBZ - BOARD EVALUATION FOR AD9233
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SERIAL PORT INTERFACE (SPI)
The AD9233 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. This provides the user added
flexibility and customization depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
are further divided into fields, as documented in the Memory
Map section. For detailed operational information, see the
Interfacing to High Speed ADCs via SPI User
CONFIGURATION USING THE SPI
As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual-purpose pin allows
data to be sent and read from the internal ADC memory map
registers. The CSB pin is an active low control that enables or
disables the read and write cycles.
Table 13. Serial Port Interface Pins
Mnemonic
SCLK/DFS
SDIO/DCS
CSB
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. Figure 57 and
Table 14 provide an example of the serial timing and its
definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, permanently enabling the device (this is
called streaming). The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high
during power up, SPI functions are placed in a high impedance
mode. This mode turns on any SPI pin secondary functions. If
CSB is high at power up and then brought low to activate the
SPI, the SPI pin secondary functions are no longer available,
unless the device power is cycled.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data indicates
whether a read or write command is issued. This allows the
serial data input/output (SDIO) pin to change direction from
an input to an output.
Description
SCLK (Serial Clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
Manual.
Rev. A | Page 23 of 44
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB first or in LSB first mode. MSB first is
the default on power up and can be changed via the
configuration register. For more information, see the
to High Speed ADCs via SPI User
Table 14. SPI Timing Diagram Specifications
Name
t
t
t
t
t
t
t
HARDWARE INTERFACE
The pins described in Table 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9233. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in the Application Note AN-812.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power on, the pins are associated with a specific function.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as standalone CMOS-
compatible control pins. When the device is powered up with
the CSB chip select connected to AVDD, the serial port interface is
disabled. In this mode, it is assumed that the user intends to use
the pins as static control lines for the output data format and
duty cycle stabilizer (see Table 10). For more information, see
the
DS
DH
CLK
S
H
HI
LO
Interfacing to High Speed ADCs via SPI User
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Manual.
Manual.
AD9233
Interfacing