AD7693BRMZ Analog Devices Inc, AD7693BRMZ Datasheet - Page 21

IC ADC 16BIT 500KSPS 10-MSOP

AD7693BRMZ

Manufacturer Part Number
AD7693BRMZ
Description
IC ADC 16BIT 500KSPS 10-MSOP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of AD7693BRMZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
16
Sampling Rate (per Second)
500k
Number Of Converters
1
Power Dissipation (max)
21.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-TFSOP (0.118", 3.00mm Width)
Resolution (bits)
16bit
Input Channel Type
Differential
Supply Voltage Range - Analogue
4.5V To 5.5V
Supply Voltage Range - Digital
2.3V To 5.8V, 1.8V To 5.8V
No.
RoHS Compliant
Sampling Rate
500kSPS
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7693CBZ - BOARD EVALUATION FOR AD7693
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7693BRMZ
Manufacturer:
ADI
Quantity:
1 000
Part Number:
AD7693BRMZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7693BRMZ-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7693BRMZ-RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7693BRMZRL7
Manufacturer:
ADI
Quantity:
1 000
Part Number:
AD7693BRMZRL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7693s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
SDO
ACQUISITION
SDI
A
t
HSCKCNV
= SDI
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7693
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
CNV
SCK
A
D
D
1
A
B
15
15
t
SSDISCK
SDO
D
D
2
A
B
14
14
D
D
3
A
B
13
13
Rev. 0 | Page 21 of 24
t
SCKL
SDI
t
HSDISCK
14
AD7693
CNV
SCK
B
t
D
D
15
CYC
A
B
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
1
1
ACQUISITION
t
SDO
SCK
t
SCKH
t
D
D
ACQ
16
A
B
0
0
D
17
A
15
CONVERT
DATA IN
CLK
D
DIGITAL HOST
18
A
14
30
D
31
A
1
D
32
A
0
AD7693

Related parts for AD7693BRMZ