AD7712ANZ Analog Devices Inc, AD7712ANZ Datasheet - Page 22

• Manufacturer Part Number: AD7712ANZ
• Description: IC ADC SIGNAL COND LC2MOS 24-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7712ANZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 5V To 10V
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply Current: 4.5mA
• No.: RoHS Compliant
• Sampling Rate: 19.5kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7712
Figure 13a shows a read operation from the AD7712 where
RFS remains low for the duration of the data word transmis-
sion. With DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the DRDY line high. This rising edge of DRDY turns off
the serial data output.
Figure 13b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and
returns low again to access the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 13b. External Clocking Mode, Output Data Read Operation ( RFS Returns High during Read Operation)
SDATA (O)
SDATA (O)
DRDY (O)
DRDY (O)
SCLK (I)
SCLK (I)
RFS (I)
RFS (I)
A0 (I)
A0 (I)
Figure 13a. External Clocking Mode, Output Data Read Operation
t
20
t
t
20
22
t
22
t
t
24
24
t
t
MSB
26
25
MSB
t
25
–22–
t
27
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when RFS returns high in the middle
of transferring a word.
RFS should return high during a low time of SCLK. On the
rising edge of RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data-word
are read from the AD7712, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N + 1) may appear on the data bus
before RFS goes high. When RFS returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as per
Figure 13a.
BIT N
t
26
THREE-STATE
t
t
27
30
t
31
LSB
t
24
t
29
t
21
BIT N+1
t
28
t
THREE-STATE
23
t
25
REV. F