AD7856KR-REEL Analog Devices Inc, AD7856KR-REEL Datasheet - Page 22

• Manufacturer Part Number: AD7856KR-REEL
• Description: IC ADC 14BIT 8CH 5V 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7856KR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 14
• Sampling Rate (per Second): 285k
• Data Interface: 8051, QSPI™, Serial, SPI™ µP
• Number Of Converters: 2
• Power Dissipation (max): 89.25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)

AD7856
is initiated. Typical figures are given in Table VIII. The timing
diagrams for the other self-calibration options will be similar to
that outlined in Figure 25.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7856 as well as calibrate the errors of the
AD7856 itself. The maximum calibration range specified for the
system offset errors is 3.75% of V
for the system gain errors is 1.875% of V
worst case conditions the maximum allowable system offset
voltage applied between AIN(+) and AIN(–) would be 0.0375
mum allowable system offset voltage applied between the AIN(+)
and AIN(–) pins for the calibration to adjust out this error is
or 0.05
maximum allowable system full-scale voltage that can be applied
between AIN(+) and AIN(–) for the calibration to adjust out
this error is V
+ 0.01875
AIN(–)). If the system offset or system gain errors are outside
the ranges mentioned the system calibration algorithm will
reduce the errors as much as the trim range allows.
Figures 26 through 28 illustrate why a specific type of system
calibration might be used. Figure 26 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upward by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
Figure 27 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for by a system gain calibration.
SYS OFFSET
V
0.05
V
REF
BUSY (O/P)
REF
Figure 25. Timing Diagram for Full-Self Calibration
– 1LSB
AGND
CAL (I/P)
MAX SYSTEM OFFSET
, but under typical conditions this means that the maxi-
IS
V
V
REF
REF
5% OF V
Figure 26. System Offset Calibration
V
REF
(i.e., the AIN(+) can be 0.05 V
REF
below AIN(–)). For the System gain error the
ANALOG
INPUT
RANGE
REF
above AIN(–) or V
0.01875
t
1
t
15
SYSTEM OFFSET
CALIBRATION
V
REF
t
t
t
1
15
CAL
V
REF
= 100ns MIN,
= 2.5
REF
(i.e., the AIN(+) can be V
= 250026
REF
+ SYS OFFSET
SYS OFFSET
but typically is 5% and
V
t
t
CLKIN
CAL
– 0.01875
MAX SYSTEM FULL SCALE
REF
IS
REF
AGND
– 1LSB
t
CLKIN
MAX,
MAX SYSTEM OFFSET
1.875% FROM V
. Therefore, under
REF
IS
5% OF V
above AIN(–)
V
REF
ANALOG
INPUT
RANGE
REF
REF
above
REF
–22–
Finally, in Figure 28 both the system offset and gain are ac-
counted for by the system offset followed by a system gain cali-
bration. First, the analog input range is shifted upward by the
positive system offset and then the analog input range is ad-
justed at the top end to account for the system full scale.
System Gain and Offset Interaction
The inherent architecture of the AD7856 leads to an interaction
between the system offset and gain errors when a system calibra-
tion is performed. Therefore, it is recommended to perform the
cycle of a system offset calibration followed by a system gain
calibration twice. Separate system offset and system gain cali-
brations reduce the offset and gain errors to at least the 14-bit
level. By performing a system offset CAL first and a system gain
calibration second, priority is given to reducing the gain error to
zero before reducing the offset error to zero. If the system errors
are small, a system offset calibration would be performed, fol-
lowed by a system gain calibration. If the systems errors are
large (close to the specified limits of the calibration range), this
cycle would be repeated twice to ensure that the offset and gain
errors were reduced to at least the 14-bit level. The advantage of
doing separate system offset and system gain calibrations is that
the user has more control over when the analog inputs need to
be at the required levels, and the CONVST signal does not have
to be used.
Alternatively, a system (gain + offset) calibration can be
performed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the 14-
bit level. For the system (gain + offset) calibration priority is
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the sys-
tem errors are large (close to the specified limits of the calibra-
tion range) three system (gain + offset) calibrations may be
SYS OFFSET
V
V
REF
REF
MAX SYSTEM FULL SCALE
IS
MAX SYSTEM FULL SCALE
SYS FS
SYS FS
– 1LSB
– 1LSB
AGND
IS
AGND
MAX SYSTEM OFFSET
1.875% FROM V
Figure 28. System (Gain + Offset) Calibration
IS
1.875% FROM V
5% OF V
Figure 27. System Gain Calibration
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
REF
REF
REF
SYSTEM OFFSET
CALIBRATION
SYSTEM GAIN
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
CALIBRATION
V
REF
+ SYS OFFSET
SYS OFFSET
V
V
REF
REF
MAX SYSTEM FULL SCALE
IS
SYS FS
MAX SYSTEM FULL SCALE
AGND
– 1LSB
SYS FS
– 1LSB
IS
AGND
MAX SYSTEM OFFSET
1.875% FROM V
IS
1.875% FROM V
5% OF V
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
REF
REF
REV. A
REF