AD7708BRUZ Analog Devices Inc, AD7708BRUZ Datasheet - Page 25

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AD7708BRUZ

Manufacturer Part Number
AD7708BRUZ
Description
IC ADC 16BIT R-R 8/10CH 28-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7708BRUZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
16
Sampling Rate (per Second)
1.37k
Number Of Converters
1
Power Dissipation (max)
3.84mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP (0.173", 4.40mm Width)
Resolution (bits)
16bit
Sampling Rate
1.4kSPS
Input Channel Type
Differential, Single Ended
Supply Current
1.1mA
Digital Ic Case Style
TSSOP
No. Of Pins
28
Number Of Elements
1
Resolution
16Bit
Architecture
Delta-Sigma
Sample Rate
1.365KSPS
Input Polarity
Bipolar
Input Type
Voltage
Rated Input Volt
±2.56V
Differential Input
Yes
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
3/5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Integral Nonlinearity Error
±15ppm of FSR
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7708EBZ - BOARD EVAL FOR AD7708
Lead Free Status / Rohs Status
Compliant

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Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0)
The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or write
operation, the type of read operation, and on which register this operation takes place. For read or write operations, once the subse-
quent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the
Communications Register. This is the default state of the interface and, on power-up or after a RESET, the AD7708/AD7718 is in
this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a
write operation of at least 32 serial clock cycles with DIN high returns the AD7708/AD7718 to this default state by resetting the part.
Table XII outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting
the bits are in the Communications Register. CR7 denotes the first bit of the data stream.
Bit
Location
CR7
CR6
CR5
CR4
CR3–CR0
W
E
C
N
R
7
(
) 0
Bit
Mnemonic
WEN
R/W
0
0
A3–A0
/ R W
C
A3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R
(
6
) 0
Description
Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register
actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis
ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the
next seven bits will be loaded to the Communications Register.
A zero in this bit location indicates that the next operation will be a write to a specified register. A one in
this position indicates that the next operation will be a read from the designated register.
A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718.
A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718.
Register Address Bits. These address bits are used to select which of the AD7708/AD7718’s registers are
being accessed during this serial interface communication. A3 is the MSB of the three selection bits.
A2
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
C
(
R
) 0
5
A1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table XII. Communications Register Bit Designations
Table XIII. Register Selection Table
A0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
0
R
(
) 0
4
Register
Communications Register during a Write Operation
Status Register during a Read Operation
Mode Register
ADC Control Register
Filter Register
ADC Data Register
ADC Offset Register
ADC Gain Register
I/O Control Register
Undefined
Undefined
Undefined
Undefined
Test 1 Register
Test 2 Register
Undefined
ID Register
A
C
3
R
(
3
) 0
A
C
2
R
(
2
) 0
A
C
1
R
(
1
) 0
AD7708/AD7718
A
C
0
R
(
0
) 0

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