LTC2408IG#PBF Linear Technology, LTC2408IG#PBF Datasheet - Page 19

• Manufacturer Part Number: LTC2408IG#PBF
• Description: IC A/D CONV 24BIT 8-CHAN 28-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2408IG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.008KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 6.188V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: 1LSB(Typ)
• Integral Nonlinearity Error: 15ppm of Vref
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS
SCK/CLK
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 32nd falling edge of SCK, see Figure 9. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 32 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.
CONVERTER
CSADC/
CSMUX
SCK/CLK
SDO
CSADC/
CSMUX
D
STATE
IN
SDO
D
IN
TEST EOC
TEST EOC
CONV
DON’T CARE
Hi-Z
U
TEST EOC
TEST EOC
Figure 9. External Serial Clock with Reduced Data Output Length Timing Diagram
INFORMATION
SLEEP
U
Hi-Z
EN
Figure 8. Use of Look Ahead to Program Multiplexer After Data Output
D2
BIT31
D1
Hi-Z
W
BIT30
D0
DON’T CARE
BIT29
SIG
BIT28
EXR
TO 1.12V
U
–0.12V
BIT27 BIT26
MSB
DATA OUTPUT
TO V
2.7V TO 5.5V
0.1V
REF
REF
CC
BIT31
V
V
CH0
TO CH7
MUXOUT
ADCIN
GND
LTC2404/LTC2408
CC
REF
BIT4
LSB
BIT30
Internal Serial Clock
This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 10. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
BIT29
SIG
CSMUX
CSADC
SDO
SCK
CLK
D
F
BIT28
IN
SUB
EXR
LSB
BIT0
O
BIT27 BIT26
MSB
EN
CS
SCK
INTERNAL CALIBRATION
V
CC
D2
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
66ms LOOK AHEAD
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
DON’T CARE
D1
LTC2404/LTC2408
BIT9
D0
DON’T CARE
BIT8
LSB
CONVERSION ON SELECTED CHANNEL
66ms CONVERT
19
24048 F08
24048 F09