CS5340-DZZ Cirrus Logic Inc, CS5340-DZZ Datasheet - Page 3

• Manufacturer Part Number: CS5340-DZZ
• Description: IC ADC AUD 101DB 200KHZ 16-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5340-DZZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 3.1V To 5.25V
• Supply Current: 21mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1544 - BOARD EVAL FOR CS5340 STEREO ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1686

DS601F2
LIST OF FIGURES
LIST OF TABLES
Figure 1.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 2.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8
Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8
Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9
Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9
Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9
Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9
Figure 12.Quad-Speed Mode Passband Ripple ......................................................................................... 9
Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12
Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12
Figure 15.Master Mode, I²S SAI ................................................................................................................ 12
Figure 16.Slave Mode, I²S SAI .................................................................................................................. 12
Figure 17.Typical Connection Diagram ..................................................................................................... 14
Figure 18.CS5340 Master Mode Clocking ................................................................................................ 16
Figure 19.I²S Serial Audio Interface .......................................................................................................... 17
Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17
Figure 21.CS5340 Recommended Analog Input Buffer ............................................................................ 18
Figure 22.CS5340 THD+N versus Frequency .......................................................................................... 19
Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 15
Table 2. CS5340 Mode Control ................................................................................................................. 15
Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
Confidential Draft
3/11/08
CS5340
3