MAX1238EEE+ Maxim Integrated Products, MAX1238EEE+ Datasheet - Page 13

• Manufacturer Part Number: MAX1238EEE+
• Description: IC ADC 12-BIT 94KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1238EEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 666.7mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 12
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 12 bit
• Interface Type: I2C
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A write cycle begins with the bus master issuing a
START condition followed by seven address bits (Figure
7) and a write bit (R/W = 0). If the address byte is suc-
cessfully received, the MAX1236–MAX1239 (slave)
issues an acknowledge. The master then writes to the
slave. The slave recognizes the received byte as the
set-up byte (Table 1) if the most significant bit (MSB) is
1. If the MSB is 0, the slave recognizes that byte as the
Figure 9. Write Cycle
Table 1. Setup Byte Format
(MSB)
BIT 7
REG
BIT
7
6
5
4
3
2
1
0
Configuration/Setup Bytes (Write Cycle)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
______________________________________________________________________________________
BIP/UNI
NAME
BIT 6
SEL2
SEL2
SEL1
SEL0
REG
CLK
RST
X
A. ONE-BYTE WRITE CYCLE
B. TWO-BYTE WRITE CYCLE
S
S
1
1
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at
power-up.
1 = external clock, 0 = internal clock. Default to 0 at power-up.
1 = bipolar, 0 = unipolar. Default to 0 at power-up (see the Unipolar/Bipolar section).
1= no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t care, can be set to 1 or 0.
7
7
BIT 5
SEL1
SETUP OR CONFIGURATION BYTE
SETUP OR CONFIGURATION BYTE
MSB DETERMINES WHETHER
MSB DETERMINES WHETHER
W
W
1 1
1 1
A
A
CONFIGURATION BYTE
CONFIGURATION BYTE
SETUP OR
SETUP OR
BIT 4
SEL0
8
8
A
A
1
1
configuration byte (Table 2). The master can write either
one or two bytes to the slave in any order (setup byte,
then configuration byte; configuration byte, then setup
byte; setup byte or configuration byte only; Figure 9). If
the slave receives a byte successfully, it issues an
acknowledge. The master ends the write cycle by issu-
ing a STOP condition or a repeated START condition.
When operating in HS-mode, a STOP condition returns
the bus into F/S-mode (see the HS-Mode section).
P or Sr
CONFIGURATION BYTE
BIT 3
CLK
1
SETUP OR
DESCRIPTION
8
NUMBER OF BITS
BIP/UNI
BIT 2
A
1
P or Sr
1
NUMBER OF BITS
BIT 1
RST
(LSB)
BIT 0
X
13