AD7999YRJZ-1500RL7 Analog Devices Inc, AD7999YRJZ-1500RL7 Datasheet - Page 10

• Manufacturer Part Number: AD7999YRJZ-1500RL7
• Description: IC ADC 8BIT 4CH SAR I2C SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD7999YRJZ-1500RL7

• Data Interface: I²C, Serial
• Design Resources: Using AD8599 as an Ultralow Distortion Driver for the AD7999 (CN0045)
• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 4.68mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Resolution (bits): 8bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 850µA
• No. Of Pins: 8
• Operating Temperature Range: -40°C To
• Sampling Rate: 140kSPS
• Digital Ic Case Style: SOT-23
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7999YRJZ-1500RL7TR

AD7991/AD7995/AD7999
Parameter
t
t
t
t
t
t
1
2
3
10
11
11A
12
SP
POWER-UP
Functionality is tested during production.
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
For 3 V supplies, the maximum hold time with
1
SCL
SDA
S = START CONDITION
P = STOP CONDITION
Conditions
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
P
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
t
= 100 pF maximum
= 400 pF maximum
= 100 pF maximum
= 400 pF maximum
= 100 pF maximum
= 400 pF maximum
= 100 pF maximum
= 400 pF maximum
7
S
t
6
t
2
t
11
C
t
4
B
= 100 pF maximum is 100 ns maximum.
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
0
Min
10
20
10
20
10
20
10
20
0
Figure 2. 2-Wire Serial Interface Timing Diagram
Limit at t
B
B
B
B
t
1
t
12
Typ
0.6
t
MIN
Rev. B | Page 10 of 28
3
, t
MAX
Max
300
300
80
160
1000
300
40
80
1000
300
80
160
300
300
40
80
50
10
ns
μs
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
t
5
t
10
Description
t
t
t
start condition and after an acknowledge bit
t
Pulse width of the suppressed spike
Power-up and acquisition time
FDA
RCL
RCL1
FCL
t
6
, rise time of the SCL signal
, fall time of the SCL signal
, fall time of the SDA signal
, rise time of the SCL signal after a repeated
t
8
P
t
9