LTC1864CMS8#PBF Linear Technology, LTC1864CMS8#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC1864CMS8#PBF
• Description: IC A/D CONV 1CH 16BIT 8-MSOP
• Manufacturer: Linear Technology

Specifications of LTC1864CMS8#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 400mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t
fi nished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CONV
SDO
SCK
•
•
•
Figure 2. LTC1864 Transfer Curve
t
CONV
*V
IN
CONV
= IN
+
– IN
Hi-Z
, the conversion is
–
Figure 1. LTC1864 Operating Sequence
SLEEP MODE
18645 F02
V
IN
*
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
and “IN
IN
equals V
“IN
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and V
span will result on “IN
Reference Input
The voltage on the reference input of the LTC1864 defi nes
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V
–
–
B15 B14
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
equals zero. Full scale occurs when IN
” inputs are sampled at the same time, so common
1
V
IN
2
t
–
suCONV
= 0V TO V
Figure 3. LTC1864 with Rail-to-Rail Input Span
B13
REF
” inputs. A zero code will occur when IN
3
B12
4
minus 1LSB. See Figure 2. Both the “IN
B11
CC
5
B10
1
2
3
4
6
B9
V
IN
IN
GND
7
REF
REF
+
–
LTC1864/LTC1865
t
LTC1864
SMPL
B8
8
+
B7
is tied to V
CONV
” as shown in Figure 3.
9
SDO
SCK
V
1μF
B6
CC
10
B5
18645 F03
11
8
7
6
5
B4
12
B3
V
13
CC
CC
B2
14
, a rail-to-rail input
B1
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
15
CC
18645 F01
B0*
16
to 1V.
Hi-Z
+
minus IN
+
13
minus
+
” and
18645fb
+
–
”
–
”