MCP3551-E/SN Microchip Technology, MCP3551-E/SN Datasheet - Page 13

• Manufacturer Part Number: MCP3551-E/SN
• Description: IC ADC 22BIT 2.7V 1CH SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP3551-E/SN

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Bits: 22
• Sampling Rate (per Second): 13.75
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Architecture: Delta-Sigma
• Conversion Rate: 0.014 KSPs
• Input Type: Voltage
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP355XDV-MS1 - BOARD DEV SENSOR APP MCP355XMCP355XDM-TAS - BOARD DEMO TINY APP SNSR MCP355X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.1
The converter core of the MCP3550/1/3 devices is a
third-order delta-sigma modulator with automatic gain
and offset error calibrations. The modulator uses a 1-bit
DAC structure. The delta-sigma modulator processes
the sampled charges through switched capacitor
structures controlled by a very low drift oscillator for
reduced clock jitter.
During the conversion process, the modulator outputs
a bit stream with the bit frequency equivalent to the
f
implemented in the modulator ensures very high
resolution and high averaging factor to achieve low-
noise specifications. The bit stream output of the mod-
ulator is then processed by the digital decimation filter
in order to provide a 22-bit output code at a data rate of
12.5 Hz for the MCP3550-50, 15 Hz for the MCP3550-
60, 13.75 Hz for the MCP3551 and 60 Hz for the
MCP3553. Since the oversampling ratio is lower with
the MCP3553 device, a much higher output data rate is
achieved while still achieving 20 bits No Missing Codes
(NMC) and 20.6 ENOB.
A self-calibration of offset and gain occurs at the onset
of every conversion. The conversion data available at
the output of the device is always calibrated for offset
and gain through this process. This offset and gain
auto-calibration is performed internally and has no
impact on the speed of the converter since the offset
and gain errors are calibrated in real-time during the
conversion. The real-time offset and gain calibration
schemes do not affect the conversion process.
TABLE 4-1:
© 2007 Microchip Technology Inc.
OSC
MCP3550-50
MCP3550-60
MCP3551
MCP3553
Note:
/4 (see Table 4-1). The high oversampling
MCP3550/1/3 Delta-Sigma
Modulator with Internal Offset and
Gain Calibration
Device
For the first conversion after exiting Shutdown, t
the conversion is complete and the RDY (Ready) flag appears on SDO/RDY.
DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE
Output Data
Rate (t
80.00 ms
66.67 ms
72.73 ms
16.67 ms
(Note)
CONV
)
(µV
Output
Noise
2.5
2.5
2.5
RMS
6
)
Primary
Notch
(Hz)
CONV
240
50
60
55
4.2
The MCP3550/1/3 devices include a digital decimation
filter, which is a fourth-order modified SINC filter. This
filter averages the incoming bit stream from the modu-
lator and outputs a 22-bit conversion word in binary
two's complement. When all bits have been processed
by the filter, the output code is ready for SPI communi-
cation, the RDY flag is set on the SDO/RDY pin and all
the internal registers are reset in order to process the
next conversion.
Like the commonly used SINC filter, the modified SINC
filter in the MCP3550/1/3 family has the main notch
frequency located at f
stream sample frequency. OSR is the Oversampling
Ratio and L is the order of the filter.
The MCP3550-50 device has the main filter notch
located at 50 Hz. For the MCP3550-60 device, the
notch is located at 60 Hz. The MCP3551 device has its
notch located at 55 Hz, and for the MCP3553 device,
the main notch is located at 240 Hz, with an OSR of
128. (see Table 4-1 for rejection performance).
The digital decimation SINC filter has been modified in
order to offer staggered zeros in its transfer function.
This modification is intended to widen the main notch in
order to be less sensitive to oscillator deviation or line-
frequency drift. The MCP3551 filter has staggered
zeros spread in order to reject both 50 Hz and 60 Hz
line frequencies simultaneously (see Figure 4-2).
must include an additional 144 f
Frequency
25600 Hz
30720 Hz
28160 Hz
30720 Hz
Sample
Digital Filter
(f
S
)
122.88 kHz
122.88 kHz
112.64 kHz
MCP3550/1/3
102.4 kHz
Internal
Clock
S
f
OSC
/(OSR*L), where f
50/60 Hz Rejection
82 dB at 50 Hz and
OSC
-82 dB min. from
48 Hz to 63 Hz. -
-88 dB at 60 Hz
-120 dB min. at
-120 dB min. at
Not Applicable
DS21950D-page 13
periods before
50 Hz
60 Hz
S
is the bit