MCP3221A5T-I/OT Microchip Technology, MCP3221A5T-I/OT Datasheet - Page 15

• Manufacturer Part Number: MCP3221A5T-I/OT
• Description: IC ADC 12BIT 2.7V 1CH LP SOT235
• Manufacturer: Microchip Technology

Specifications of MCP3221A5T-I/OT

• Package / Case: SC-74A, SOT-753
• Number Of Bits: 12
• Sampling Rate (per Second): 22.3k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Architecture: SAR
• Conversion Rate: 22.3 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: VSUPEV2 - BOARD EVAL FOR MCP4022,4023,4024MXSIGDM - BOARD DEMO PICTAIL MIXED SIGNAL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MCP3221A5T-I/OT; MCP3221A5T-I/OTTR

5.0
5.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (refer to Figure 5-1).
5.1.1
Both data and clock lines remain high.
5.1.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a START condition. All
commands must be preceded by a START condition.
5.1.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a STOP condition. All
operations must be ended with a STOP condition.
5.1.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the clock signal’s high period.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 5-1:
© 2006 Microchip Technology Inc.
SDA
SCL
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a START or STOP condition.
(A)
SERIAL COMMUNICATIONS
I
2
C Bus Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
DATA VALID (D)
CONDITION
START
(B)
Data Transfer Sequence on the Serial Bus.
ACKNOWLEDGE
ADDRESS OR
VALID
(D)
TO CHANGE
ALLOWED
DATA
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
unlimited.
5.1.5
Each receiving device, when addressed, is obliged to
generate an acknowledge bit after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge-related clock pulse. Setup
and hold times must be taken into account. During
reads, a master device must signal an end of data to
the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave (NAK).
In this case, the slave (MCP3221) will release the bus
to allow the master device to generate the STOP
condition.
The MCP3221 supports a bidirectional, 2-wire bus and
data transmission protocol. The device that sends data
onto the bus is the transmitter and the device receiving
data is the receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the MCP3221 works as a slave
device. Both master and slave devices can operate as
either transmitter or receiver, but the master device
determines which mode is activated.
ACKNOWLEDGE
(D)
MCP3221
DS21732C-page 15
CONDITION
STOP
(C)
(A)