AD73322LYR Analog Devices Inc, AD73322LYR Datasheet - Page 25

• Manufacturer Part Number: AD73322LYR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LYR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

DATA MODE
Once the device has been configured by programming the
correct settings to the various control registers, the device
may exit program mode and enter data mode. This is done
by programming the DATA/ PGM (CRA:0) bit to a 1 and
MM (CRA:1) to 0. Once the device is in data mode, the 16-bit
input data frame is interpreted as DAC data rather than a
control frame. This data is therefore loaded directly to the DAC
register. As Figure 20 shows, because the entire input data frame
contains DAC data in data mode, the device relies on counting
the number of input frame syncs received at the SDIFS pin.
When that number equals the device count stored in the device
count field of CRA, the device knows that the present data
frame being received is its own DAC update data. When the
device is in normal data mode (that is, mixed mode disabled), it
must receive a hardware reset to reprogram any of the control
register settings.
In a single AD73322L configuration, each 16-bit data frame
sent from the DSP to the device is interpreted as DAC data, but
it is necessary to send two DAC words per sample period in
order to ensure the DAC update. Also, as the device count
setting defaults to 1, it must be set to 2 (001b) to ensure correct
update of both DACs on the AD73322L.
The section DAC Timing Control Example details the initial-
ization and operation of an AD73322L in normal data mode.
SDOFS
SDIFS
SCLK
SDO
SDI
SE
Figure 21. Interface Signal Timing for Data Mode Operation
ADC SAMPLE WORD
DAC DATA WORD
(DEVICE 2)
(DEVICE 2)
ADC SAMPLE WORD
DAC DATA WORD
(DEVICE 1)
(DEVICE 1)
Rev. A | Page 25 of 48
MIXED PROGRAM/DATA MODE
This mode allows the user to send control words to the device
along with the DAC data. This permits adaptive control of the
device where control of the input/output gains, etc., can be
affected by interleaving control words along with the normal
flow of DAC data. The standard data frame remains 16 bits, but
the MSB is used as a flag bit to indicate whether the remaining
15 bits of the frame represent DAC data or control information.
In the case of DAC data, the 15 bits are loaded with MSB
justification and LSB set to 0 to the DAC register. Mixed mode
is enabled by setting the MM bit (CRA:1) to 1 and the
DATA/ PGM bit (CRA:0) to 1. In the case where control setting
changes are required during normal operation, this mode
allows the ability to load both control and data information
with the slight inconvenience of formatting the data. Note that
the output samples from the ADC will also have the MSB set to
zero to indicate it is a data-word.
The section Configuring an AD73322L to Operate in Mixed
Mode details the initialization and operation of an AD73322L
operating in mixed mode. Note that it is not essential to load
the control registers in Program Mode before setting mixed
mode active. It is also possible to initiate mixed mode by
programming CRA with the first control word and then
interleaving control words with DAC data.
DIGITAL LOOP-BACK MODE
This mode can be used for diagnostic purposes, allowing the
user to feed the ADC samples from the ADC register directly to
the DAC register. This forms a loop-back of the analog input to
the analog output by reconstructing the encoded signal using
the decoder channel. The serial interface continues to work,
which allows the user to control gain settings, SCLK frequency,
sample rate, etc. Only when DLB is enabled with mixed mode
operation can the user disable the DLB—otherwise the device
must be reset.
SPORT LOOP-BACK MODE
This mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the devices and
have them returned back unchanged after a delay of 16 SCLK
cycles. The frame sync and data-word that are sent to the device
are returned via the output port. Again, SLB mode can only be
disabled when used in conjunction with mixed mode, otherwise
the device must be reset.
AD73322L