AD73322LAR-REEL Analog Devices Inc, AD73322LAR-REEL Datasheet - Page 11

• Manufacturer Part Number: AD73322LAR-REEL
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

Mnemonic
SCLK
MCLK
SDO
SDOFS
SDIFS
SDI
SE
AGND1
AVDD1
VOUTP2
VOUTN2
VOUTP1
VOUTN1
VINP2
VFBP2
VINN2
VFBN2
Function
Master Clock Input. MCLK is driven from an external clock signal.
Analog Ground/Substrate Connection.
Analog Power Supply Connection.
Analog Output from the Positive Terminal of Output Channel 2.
Analog Output from the Negative Terminal of Output Channel 2.
Analog Output from the Positive Terminal of Output Channel 1.
Analog Output from the Negative Terminal of Output Channel 1.
Analog Input to the inverting input amplifier on Channel 2’s positive input.
Analog Input to the inverting input amplifier on Channel 2’s negative input.
Serial Clock Output. This rate determines the serial transfer rate to/from the codec. It is used to clock data or control
information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK)
divided by an integer number—this integer number being the product of the external master clock rate divider and the serial
clock rate divider.
Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive edge of
SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first
bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before the first bit
(MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low.
Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK.
SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are
three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is
brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however,
the timing counters and other internal registers are at their reset values.
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input amplifiers are
bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are
bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
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AD73322L