AD9878BST Analog Devices Inc, AD9878BST Datasheet
AD9878BST
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AD9878BST Summary of contents
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FEATURES Low cost 3.3 V CMOS MxFE™ for broadband applications DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant 232 MHz quadrature digital upconverter 12-bit direct IF DAC (TxDAC+® MHz carrier frequency DDS Programmable sampling clock rates Analog Tx output level ...
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AD9878 TABLE OF CONTENTS Electrical Characteristics ................................................................. 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 13 Register ...
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REVISION HISTORY 3/05—Rev Rev. A Changed OSCOUT to REFCLK.................................................. Universal Changes to Electrical Characteristics ........................................................4 Changes to Pin Configuration and Function Descriptions....................8 Changes to ∑-∆ Output Signals (Figure 32)............................................27 Change to ∑-∆ RC Filter (Figure 33) .......................................................27 Changes ...
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AD9878 ELECTRICAL CHARACTERISTICS V = 3.3 V ± 5 3.3 V ± 10 OSCIN R = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load. SET Table 1. PARAMETER OSCIN and XTAL CHARACTERISTICS Frequency Range ...
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PARAMETER Dynamic Performance (A = −0.5 dBFS MHz) IN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) 12-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input ...
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AD9878 PARAMETER TIMING CHARACTERISTICS (10 pF Load) Wake-Up Time Minimum RESET Pulse Width Low Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency, f MCLK TxSYNC/TxIQ Setup Time TxSYNC/TxIQ Hold Time MCLK Rising Edge to ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Power Supply ( AVDD DVDD DRVDD Digital Output Current Digital Inputs Analog Inputs Operating Temperature Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec) ESD CAUTION ESD (electrostatic ...
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AD9878 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 99 100 DRGND 1 DRVDD 2 (MSB) IF12(11) 3 IF12(10) 4 IF12(9) 5 IF12(8) 6 IF12(7) 7 IF12(6) 8 IF12(5) 9 IF12(4) 10 IF12(3) 11 IF12(2) 12 IF12(1) 13 IF12(0) 14 (MSB) IF10(4) 15 ...
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Pin No. Mnemonic 44 SDO 45 DGNDTx 46 DVDDTx 47 PWRDN 48 REFIO 49 FSADJ 50 AGNDTx 51, 52 Tx−, Tx+ 53 AVDDTx 54 DGNDPLL 55 DVDDPLL 56 AVDDPLL 57 PLLFILT 58 AGNDPLL 59 DGNDOSC 60 XTAL 61 OSCIN 62 ...
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AD9878 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (MHz) Figure 3. Dual-Sideband Spectral Plot kΩ mA), RBW = ...
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FREQUENCY (MHz) Figure 9. Single Sideband @ 42 MHz MHz MHz kΩ ...
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AD9878 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –50 –40 –30 –20 – FREQUENCY (MHz) Figure 15. Single Sideband @ 65 MHz MHz kΩ ...
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TERMINOLOGY Differential Nonlinearity Error (DNL, No Missing Codes) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. No missing codes indicates that all of the ADC codes must be ...
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AD9878 REGISTER BIT DEFINITIONS Table 4. Register Map Address (Hex) Bit 7 Bit 6 Bit 5 0x00 SDIO LSB Reset bidirectional first 0x01 PLL lock detect 0x02 Power down Power Power PLL down down DAC digital Tx Tx 0x03 Video ...
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REGISTER 0x00—INITIALIZATION Bits OSCIN Multiplier This register field is used to program the on-chip clock multiplier that generates the chip’s high frequency system clock For example, to multiply the external crystal clock f SYSCLK by ...
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AD9878 REGISTER 0x07—VIDEO INPUT CONFIGURATION Bits [6:0]: Clamp Level Control Value The 7-bit clamp-level control value is used to set an offset to the automatic clamp-level control loop. The actual ADC output has a clamp-level offset equal to 16 times ...
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Setting this bit to 0 (default) configures the serial interface to be compatible with AD8321/AD8323/AD8328 variable cable gain amplifiers. Setting this bit to 1 configures the serial interface to be compatible with AD8322/AD8327 variable cable gain amplifiers. Bit 5: Profile ...
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AD9878 SERIAL INTERFACE FOR REGISTER CONTROL The AD9878 serial port is a flexible, synchronous, serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9878. Single ...
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MSB/LSB TRANSFERS The AD9878 serial port can support either MSB-first or LSB-first data formats. This functionality is controlled by the LSB-first bit in Register 0x00. The AD9878 default serial port mode is MSB-first (see Figure 21), which is programmed by ...
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AD9878 THEORY OF OPERATION For a general understanding of the AD9878, refer to Figure 23, a block diagram of the device architecture. The device consists of a transmit path, receive path, and auxiliary functions, such as a PLL, a ∑-∆ ...
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MCLK TxSYNC TxI[11:6] TxI[5:0] TxIQ TRANSMIT PATH The transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit current output DAC. The maximum output current of the DAC is set by an ...
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AD9878 been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter with a raised cosine response. In such cases, an α value is used to modify the bandwidth of the ...
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Tx THROUGHPUT AND LATENCY Data inputs affect the output fairly quickly, but remain effective due to the AD9878 filter characteristics. Data transmit latency through the AD9878 is easiest to describe in terms of f cycles (4 × The ...
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AD9878 interface. The Tx gain control select bit in Register 0x0F changes the interpretation of the bits in Register 0x13, Register 0x17, Register 0x1B, and Register 0x1F. See Figure 28 and the Cable-Driver Gain Control section ...
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C4 0.1µ 100 DRGND 1 DRVDD 2 (MSB) IF12(11) 3 IF12(10) 4 IF12(9) 5 IF12(8) 6 IF12(7) 7 IF12(6) 8 IF12(5) 9 IF12(4) 10 IF12(3) 11 IF12(2) 12 IF12(1) 13 IF12(0) 14 (MSB) ...
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AD9878 POWER-UP SEQUENCE Upon initial power-up, the RESET pin should be held low until the power supply is stable (see Figure 30). Once RESET is deasserted, the AD9878 can be programmed over the serial port. The on- chip PLL requires ...
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OUTPUTS An on-chip ∑-∆ output provides a digital logic bit stream with an average duty cycle that varies between 0% and (255/256)%, depending on the programmed code, as shown in Figure 32 MCLK 256 × ...
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AD9878 Driving the Input The IF ADCs have differential switched capacitor sample-and- hold amplifier (SHA) inputs. The nominal differential input impedance is 4.0 kΩ||3 pF. This impedance can be used as the effective termination impedance when calculating filter transfer characteristics ...
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ADC VOLTAGE REFERENCES The AD9878 has three independent internal references for its 10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are designed for 2 V p-p input voltages and have their own internal reference. Figure 29 shows the proper ...
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AD9878 PCB DESIGN CONSIDERATIONS Although the AD9878 is a mixed-signal device, the part should be treated as an analog component. The on-chip digital circuitry is designed to minimize the impact of digital switching noise on the operation of the analog ...
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CC0603 RC0805 CC0805 CC0805 CC0805 RC0603 CC0603 RC0605 RC0805 RC0805 TRANSMIT DIGITAL RIBBON RA HEADER RC0805 RP1 CC0603 RCOM 1 CC0603 ...
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AD9878 PORT PARALLEL PC GND3 TSSOP24 17 74LVXC3245 VCCB 24 DVDD CA_SLEEP GND3 ...
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Figure 40. Evaluation PCB—Top Assembly Figure 41. Evaluation PCB—Bottom Assembly Rev Page AD9878 ...
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AD9878 Figure 42. Evaluation PCB Layout—Top Layer Figure 43. Evaluation PCB Layout—Bottom Layer Rev Page ...
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Figure 44. Evaluation PCB—Power Plane Figure 45. Evaluation PCB—Ground Plane Rev Page AD9878 ...
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... ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9878BST −40°C to +85°C 1 AD9878BSTZ −40°C to +85°C AD9878- Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1.60 MAX ...