ISL51002CQZ-150 Intersil, ISL51002CQZ-150 Datasheet
ISL51002CQZ-150
Specifications of ISL51002CQZ-150
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ISL51002CQZ-150 Summary of contents
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... Automatic sampling phase adjustment • 10-bit triple Analog to Digital Converters with oversampling video modes • 165MSPS maximum conversion rate (ISL51002CQZ-165) • Robust, glitchless Macrovision®-compliant sync separator • Analog VCR “Trick Mode” support • ABLC™ for perfect black level performance • ...
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... Ordering Information PART NUMBER/PART MARKING ISL51002CQZ-110 (Note) ISL51002CQZ-150 (Note) ISL51002CQZ-165 (Note) ISL51002EVALZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... MQFP Package (Notes Maximum Power Dissipation 1.2W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = A3.3 D3.3 PLLA3.3 = +0°C to +70°C, unless otherwise specified. ...
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Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f and T A SYMBOL PARAMETER Input Capacitance Full Power Bandwidth SOG INPUT CHARACTERISTICS (SOG Sync Tip Clamp SOG Pull Down V ...
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Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f and T A SYMBOL PARAMETER I Analog Supply Current, 1.8V A1.8 (Note 4) I Digital Supply Current, 3.3V D3.3 (Note 4) ...
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Timing Diagrams Data Output Setup and Hold Timing DATACLK DATACLK PIXEL DATA RGB Output Data Timing and Latency HSYNC IN ANALOG VIDEO IN DATACLK R/G/B[9:0] HS OUT YUV Output Data Timing and Latency HSYNC IN ANALOG P ...
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... Pin Configuration (MQFP, ISL51002 A1 GND SOG A3 GND VREF RED A1.8 13 SOG GND ISL51002CQZ-xxx GND VREF GREEN 21 SOG A1 GND A3 GND A 29 SOG VREF BLUE VADC D1.8 33 GND D 34 ATEST1 35 ATEST2 36 VPLL A3.3 37 GND ISL51002 102 G0 101 G1 100 D1.8 96 GND D3.3 89 GND ...
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Pin Descriptions SYMBOL Analog inputs. Red channels. AC couple through 0.1µ Analog inputs. Green channels. AC couple through 0.1µ Analog inputs. Blue channels. ...
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Pin Descriptions (Continued) SYMBOL INT Digital output, open drain, 5V tolerant. Interrupt output indicating mode change or command execution status. Pull high with a 4.7k resistor. DE 3.3V digital output. High when there is valid video data, low during horizontal ...
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Sync Flow 3 CH0 3 165 MHZ CH1 3 TRIPLE 10- BIT 3 CH2 AFE 3 CH3 SOG SOG0 SLICER A SOG1 SOG2 SOG SOG3 SLICER B HSYNC HSYNC0 SLICER A HSYNC1 HSYNC2 HSYNC HSYNC3 SLICER B VSYNC VSYNC0 SLICER ...
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Register Listing REGISTER ADDRESS (DEFAULT VALUE) STATUS AND INTERRUPT REGISTERS 0x01 Selected Input Channel Characteristics, (read only) 0x02 CH0 and CH1 Activity Status, (read only) 0x03 CH2 and CH3 Activity Status, (read only) 11 ISL51002 BITS FUNCTION NAME 1:0 SYNC ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x04 Interrupt Status, Write each bit to clear it, 0xFF to clear all. 0x05 Interrupt Mask Register, (0xFF) 12 ISL51002 BITS FUNCTION NAME 0 CH0 Sync Changed 0: No change ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) CONFIGURATION REGISTERS 0x10 Input Configuration, (0x00) 0x11 Sync Source Selection, (0x00) 0x12 Red Gain MSB, (0x55) 0x13 Red Gain LSB, (0x00) 0x14 Green Gain MSB, (0x55) 0x15 Green Gain LSB, (0x00) 0x16 Blue ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x19 Red Offset LSB, (0x00) 0x1A Green Offset MSB, (0x80) 0x1B Green Offset LSB, (0x00) 0x1C Blue Offset MSB, (0x80) 0x1D Blue Offset LSB, (0x00) 0x1E PLL Htotal MSB, (0x06) 0x1F PLL Htotal ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x27 ABLC Configuration, (0x40) 0x28 Output Format 1, (0x00) 15 ISL51002 BITS FUNCTION NAME 0 ABLC Disable 0: ABLC on (default) - use 10-bit digital offset control. 0x000 = -0x200 LSB offset, 0x3FF ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x29 Output Format 2, (0x00) 0x2A HS Width, (0x10) OUT 0x2B Output Signal Disable, (0xFF) Note: All digital outputs are tristated by default to ease multiplexing with other AFEs 0x2C Power Control, (0x00) ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x2D XTAL CLOCK FREQ, (0x19) 0x2E AFE Bandwidth, (0x0E) 0x2F HSYNC Slicer Thresholds, (0x44) All values referred to voltage at HSYNC input pin, 300mV hysteresis 0x30 SOG Slicer Thresholds, (0x66) 17 ISL51002 BITS ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x31 HSYNC/SOG Config, (0x04) 0x32 Sync Polling Control, (0x00) MEASUREMENT REGISTERS 0x40 HSYNC Period MSB, (read only) 0x41 HSYNC Period LSB, (read only) 0x42 HSYNC Width MSB, (read only) 0x43 HSYNC Width LSB, ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x44 VSYNC Period MSB, (read only) 0x45 VSYNC Period LSB, (read only) 0x46 VSYNC Width, (read only) 0x47 DE Start MSB, (0x00) 0x48 DE Start LSB, (0xF6) 0x49 DE Width MSB, (0x05) 0x4A ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x52 Phase ADJ MASK V, (0x01) 0x53 Horizontal pixel mask 1, (0x01) 0x54 Horizontal pixel mask 2, (0x01) 0x55 Phase Adjust Command Options, (0x20) 20 ISL51002 BITS FUNCTION NAME 2:0 PADJ Exclude v2 ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x56 Transition threshold, (0x0A) 0x57 Phase Adjust Data 3, (read only) 0x58 Phase Adjust Data 2, (read only) 0x59 Phase Adjust Data 1, (read only) 0x5A Phase Adjust Data 0, (read only) 0x60 ...
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Technical Highlights The ISL51002 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied ...
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The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x8000, which forces the ADC to output code 0x0000 ...
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DC RESTORATION V CLAMP DC RESTORE CLAMP DAC GENERATION R(GB VGA0 R(GB) 0 GND R(GB) 1 VGA1 R(GB) 1 GND PGA R(GB) 2 VGA2 IN R(GB) 2 GND R(GB ...
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... Intersil’s DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x74 to 0x4C. This increases the phase error gain to 100%. Because a phase ...
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The default Offset DAC range is ±127 ADC LSBs. Setting 0x27[ reduces the swing of the Offset DAC by 50%, making 1 Offset DAC LSB the weight of 1 ADC LSB. This provides the finest offset ...
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SOG activity when there actually is no SOG signal, while non-standard SOG signals and TriLevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected consequence, not all ...
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... If the databus is lightly loaded, it may be increased. Intersil’s recommendations to minimize EMI are: • Minimize the databus trace length • Minimize the databus capacitive loading. If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler’ ...
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Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a ...
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START COMMAND ISL51002 SERIAL BUS ADDRESS (REPEAT IF DESIRED) STOP COMMAND S T REGISTER SERIAL BUS A SIGNALS ADDRESS R ADDRESS FROM THE T HOST ...
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START COMMAND ISL51002 SERIAL BUS ADDRESS START COMMAND ISL51002 SERIAL BUS (REPEAT IF DESIRED) STOP COMMAND S T SERIAL BUS ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...